FOR
FOR
enCoRe™
USB CY7C63722/23
CY7C63743
Free-running Timer
11
10
9
8
7
6
5
4
3
2
1
0
1 MHz
Clock
First Edge Hold
Bit 7, Reg 0x44
Prescaler
Mux
8-bit Capture Registers
Timer A Rising Edge Time
GPIO
P0.0
Rising
Edge
Detect
Falling
Edge
Detect
Rising
Edge
Detect
Falling
Edge
Detect
Timer A Falling Edge Time
Timer B Rising Edge Time
GPIO
P0.1
Timer B Falling Edge Time
Capture A Rising Int Enable
Bit 0, Reg 0x44
Capture Timer A Interrupt Request
Capture A Falling Int Enable
Bit 1, Reg 0x44
Capture B Rising Int Enable
Bit 2, Reg 0x44
Capture Timer B Interrupt Request
Capture B Falling Int Enable
Bit 3, Reg 0x44
Figure 19-1. Capture Timers Block Diagram
The four Capture Timer Data Registers are read-only, and are shown in
through
Out of the 12-bit free running timer, the 8-bit captured in the Capture Timer Data Registers are determined by the Prescale Bit [2:0]
in the Capture Timer Configuration Register (Figure
Bit #
Bit Name
Read/Write
Reset
R
0
R
0
R
0
7
6
5
4
R
0
3
R
0
2
R
0
1
R
0
0
R
0
Capture A Rising Data
Figure 19-2. Capture Timer A-Rising, Data Register (Address 0x40)
Document #: 38-08022 Rev. **
Page 33 of 58
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