FOR
FOR
enCoRe™
USB CY7C63722/23
CY7C63743
XTALOUT
3.0
Logic Block Diagram
XTALIN/P2.1
Internal
Oscillator
Xtal
Oscillator
8-bit
RISC
Core
Wake-Up
Timer
RAM
256 Byte
12-bit
Timer
Capture
Timers
SPI
EPROM
8K Byte
Brown-out
Reset
Watch
Dog
Timer
Low
Voltage
Reset
Interrupt
Controller
USB
Engine
USB &
PS/2
Xcvr
Port 1
GPIO
Port 0
GPIO
3.3V
Regulator
VREG/P2.0
D+,D–
P1.0–P1.7
P0.0–P0.7
4.0
Pin Configurations
Top View
CY7C63723
18-pin SOIC/PDIP
P0.0
P0.1
P0.2
P0.3
P1.0
VSS
VPP
VREG/P2.0
XTALIN/P2.1
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
P0.4
P0.5
P0.6
P0.7
P1.1
D+/SCLK
D–/SDATA
VCC
XTALOUT
CY7C63743
24-pin SOIC/PDIP
P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
P1.4
P1.6
VSS
VPP
VREG/P2.0
XTALIN/P2.1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
P0.4
P0.5
P0.6
P0.7
P1.1
P1.3
P1.5
P1.7
D+/SCLK
D–/SDATA
VCC
XTALOUT
CY7C63722-XC
DIE
3
2
1
25
24
23
P0.3
P1.0
P1.2
P1.4
P1.6
VSS
4
5
6
7
8
9
P0.2
P0.1
P0.0
P0.4
P0.5
P0.6
22
21
20
19
18
P0.7
P1.1
P1.3
P1.5
P1.7
VSS 10
VPP 11
VREG 12
XTALIN/P2.1
XTALOUT
VCC
D-/SDATA
13
14
15
16
17 D+/SCLK
5.0
Pin Assignments
CY7C63723
Name
I/O
I/O
I/O
18-Pin
12
13
CY7C63743
24-Pin
15
16
CY7C63722
25-Pad
16
17
Description
USB differential data lines (D– and D+), or PS/2 clock
and data signals (SDATA and SCLK)
D–/SDATA,
D+/SCLK
P0[7:0]
1, 2, 3, 4,
1, 2, 3, 4,
1, 2, 3, 4,
GPIO Port 0 capable of sinking up to 50 mA/pin, or
15, 16, 17, 18 21, 22, 23, 24 22, 23, 24, 25 sinking controlled low or high programmable current.
Can also source 2 mA current, provide a resistive
pull-up, or serve as a high-impedance input. P0.0 and
P0.1 provide inputs to Capture Timers A and B, respec-
tively.
5, 14
5, 6, 7, 8,
5, 6, 7, 8,
IO Port 1 capable of sinking up to 50 mA/pin, or sinking
17, 18, 19, 20 18, 19, 20, 21 controlled low or high programmable current. Can also
source 2 mA current, provide a resistive pull-up, or
serve as a high-impedance input.
Page 7 of 58
P1[7:0]
I/O
Document #: 38-08022 Rev. **
CYPRESS [ CYPRESS SEMICONDUCTOR ]
