FOR
FOR
enCoRe™
USB CY7C63722/23
CY7C63743
The polarity that triggers an interrupt is controlled independently for each GPIO pin by the GPIO Interrupt Polarity Registers.
and
control the interrupt polarity of each GPIO pin.
Bit #
Bit Name
Read/Write
Reset
W
0
W
0
W
0
7
6
5
4
W
0
3
W
0
2
W
0
1
W
0
0
W
0
P0 Interrupt Polarity
Figure 21-6. Port 0 Interrupt Polarity Register (Address 0x06)
Bit [7:0]: P0[7:0] Interrupt Polarity
1 = Rising GPIO edge
0 = Falling GPIO edge
Bit #
Bit Name
Read/Write
Reset
W
0
W
0
W
0
7
6
5
4
W
0
3
W
0
2
W
0
1
W
0
0
W
0
P1 Interrupt Polarity
Figure 21-7. Port 1 Interrupt Polarity Register (Address 0x07)
Bit [7:0]: P1[7:0] Interrupt Polarity
1 = Rising GPIO edge
0 = Falling GPIO edge
Port Bit Interrupt
Polarity Register
GPIO Interrupt
Flip Flop
1
D
Q
Interrupt
Priority
Encoder
IRQout
Interrupt
Vector
OR Gate
(1 input per
GPIO pin)
GPIO
Pin
M
U
X
CLR
1 = Enable
0 = Disable
IRA
Port Bit Interrupt
Enable Register
1 = Enable
0 = Disable
Global
GPIO Interrupt
Enable
(Bit 6, Register 0x20)
Figure 21-8. GPIO Interrupt Diagram
Document #: 38-08022 Rev. **
Page 41 of 58
CYPRESS [ CYPRESS SEMICONDUCTOR ]
