FOR
FOR
enCoRe™
USB CY7C63722/23
CY7C63743
USB-PS/2 Clear
CLR
1
USB-
PS/2
Int
D
CLK
Q
Enable [0]
(Reg 0x20)
USB-PS/2 IRQ
128-µs CLR
128-µs IRQ
1-ms CLR
1-ms IRQ
EP0 CLR
EP0 IRQ
EP1 CLR
EP1 IRQ
EP2 CLR
EP2 IRQ
SPI CLR
SPI IRQ
Capture A CLR
Capture A IRQ
Capture B CLR
Capture B IRQ
GPIO CLR
GPIO IRQ
Wake-up CLR
CLR
1
Wake-up
Int
D
CLK
Q
Wake-up IRQ
Interrupt
Vector
To CPU
CPU
IRQout
IRQ Pending
(Bit 7, Reg 0xFF)
IRQ
CLR
1
EP2
Int
D
CLK
Q
Enable [2]
(Reg 0x21)
Global
Interrupt
Enable
Bit
CLR
Int Enable
Sense
(Bit 2, Reg 0xFF)
Controlled by DI, EI, and
RETI Instructions
Interrupt
Acknowledge
Enable [7]
(Reg 0x20)
Interrupt
Priority
Encoder
Figure 21-3. Interrupt Controller Logic Block Diagram
Bit #
Bit Name
Read/Write
Reset
W
0
W
0
W
0
7
6
5
4
W
0
3
W
0
2
W
0
1
W
0
0
W
0
P0 Interrupt Enable
Figure 21-4. Port 0 Interrupt Enable Register (Address 0x04)
Bit [7:0]: P0 [7:0] Interrupt Enable
1 = Enables GPIO interrupts from the corresponding input pin.
0 = Disables GPIO interrupts from the corresponding input pin.
Bit #
Bit Name
Read/Write
Reset
W
0
W
0
W
0
7
6
5
4
W
0
3
W
0
2
W
0
1
W
0
0
W
0
P1 Interrupt Enable
Figure 21-5. Port 1 Interrupt Enable Register (Address 0x05)
Bit [7:0]: P1 [7:0] Interrupt Enable
1 = Enables GPIO interrupts from the corresponding input pin.
0 = Disables GPIO interrupts from the corresponding input pin.
Document #: 38-08022 Rev. **
Page 40 of 58
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