FOR
FOR
enCoRe™ USB CY7C63722/23
CY7C63743
Parameter
TSCKH
TSCKL
TMDO
TMDO1
Description
SPI Clock High Time
SPI Clock Low Time
Min.
125
125
–25
100
Max.
Unit
ns
ns
ns
ns
Conditions
High for CPOL = 0, Low for CPOL = 1
Low for CPOL = 0, High for CPOL = 1
SCK to data valid
Master Data Output Time
50
Master Data Output Time,
Time before leading SCK edge
First bit with CPHA = 1
TMSU
TMHD
TSSU
TSHD
TSDO
TSDO1
Master Input Data Set-up time
Master Input Data Hold time
Slave Input Data Set-up Time
Slave Input Data Hold Time
Slave Data Output Time
50
50
50
50
ns
ns
ns
ns
ns
ns
100
100
SCK to data valid
Time after SS LOW to data valid
Slave Data Output Time,
First bit with CPHA = 1
TSSS
TSSH
Slave Select Set-up Time
Slave Select Hold Time
150
150
ns
ns
Before first SCK edge
After last SCK edge
.
TCYC
TCH
CLOCK
TCL
Figure 26-1. Clock Timing
TF
TR
D+
Voh
90%
90%
Vcrs
10%
10%
Vol
D−
Figure 26-2. USB Data Signal Timing
Document #: 38-08022 Rev. **
Page 51 of 58
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