PRELIMINARY
C9926
Low EMI Clock Generator for Intel 133MHz/ 2DIMM Chipset Systems
Power on Bi-Directional Pins
Power Up Condition:
Pins 2, 12, 26 are Power up bi-directional pins and are used for selecting the host frequency in p.1, table 1. During
power-up of the device, these pins are in input mode (see Fig 4, below), therefore; they are considered input select pins,
SEL(1:3) internal to the IC. After a settling time, the selection data is latch into the internal control register and these
pins become a clock output.
VDD Rail
Power Supply
Ramp
REF/SEL1(Pin 2)
PCI0/SEL3 (Pin12)
USB/SEL2 (26)
-
Hi-Z Inputs
Toggle Outputs
Select Data is latched into register, then pin becomes a REF clock output signal.
Fig.4
Vdd
R up
Strapping Resistor Options:
The power up bi-directional pins have a large value pull-
down (50KΩ+/−25KΩ), therefore, a selection “0” is the
default. If the system uses a slow power supply (over
10mS settling time), then it is recommended to use an
external Pull-down (Rdn) in order to insure a low
selection. In this case, the designer may choose one of
two configurations, see Fig.5A and B.
1K
IMI C9926
R d
Load
Bidirectional
JP1
JU MPER
Fig. 5A
R dn
5K
Fig. 5A represents an additional pull down resistor 5KΩ
connected from the pin to the power line, which allows a
faster down to a high level.
If a selection “1” is desired, then a jumper is placed on
JP1 to a 1 KΩ resistor as shown in Fig.5A. Please note
the selection resistors (Rup and Rdn) are placed before
the Damping resistor (Rd) close to the pin.
JP2
3 W ay Jum per
Vdd
3
2
1
Fig. 5B represent a single resistor 5KΩ connected to a
3-way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
R sel
5K
IMI C9926
R d
Load
Bidirectional
Fig. 5B
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07070 Rev. **
5/4/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress
Page 6 of 21
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