PRELIMINARY
C9926
Low EMI Clock Generator for Intel 133MHz/ 2DIMM Chipset Systems
Test Mode Function
Test Mode Functionality
TS#
0
SEL0
CPU
SDRAM
TCLK/2
Tri-state
3V66
PCI
DOT/USB
TCLK/2
REF
TCLK
IOAPIC
TCLK/6
Tri-state
1
0
TCLK/2
Tri-state
TCLK/3
TCLK/6
Tri-state
0
Tri-state
Table 2
Tri-state
Tri-state
Note: TCLK is a test clock over driven on the XIN input during test mode. Test Mode/Tri-state mode set during power up
and if TS# is low. Also can be set through SMBus when Byte3 Bit6 = 1, Byte0 Bit0 = 1, and Bit4 = 0 or 1.
Power Management Functions
Power Management on this device is controlled by a single pin, PD# (pin28). When PD# is high (default) the device is in
normal running mode and all signals are active.
When PD# is asserted (forced) low, the device is in shutdown (or in power down) mode and all power supplies may be
removed. When in power down, all outputs are synchronously stopped in a low state (see Fig.2 below), all PLL’s are
shut off, and the crystal oscillator is disabled. When the device is shutdown, the I²C function is also disabled.
Power Management Timing
0ns
100MHz
10ns
20ns
30ns
40ns
50ns
CPU
3V66
66MHz
33MHz
33MHz
PCI
IOAPIC
TS#/PD#
Undefined
Undefined
Undefined
SDRAM 100MHz
14.3MHz
48MHz
REF
USB
Fig.2
Power Management Current
Maximum 2.5 Volt Current
Consumption (VDDC = VDDI =2.625V)
Maximum 3.3 Volt Current Consumption
(VDD = VDDA = VDDS = 3.465V)
PD#, SEL(3:0)
0XXXX (Power down)
10000 (66MHz)
10mA
70mA
10mA
280mA
280mA
365mA
10001 (100MHz)
1001X (133MHz)
100mA
133mA
Table 3
When exiting the power down mode, the designer must supply power to the VDD pins first, a minimum of 200ms before
releasing the PD# pin high.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07070 Rev. **
5/4/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress
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