PRELIMINARY
C9926
Low EMI Clock Generator for Intel 133MHz/ 2DIMM Chipset Systems
Pin Description
PIN No.
Pin Name
PWR
VDDI
VDD
I/O TYPE
O
I/O PD
Description
47
2
2.5V IOAPIC clock output. See fig.3 p.4 for timing relationship.
This is a bi-directional pin (see app. note, p.6). At power up, it is
an input pin SEL1 for frequency selection (see table 1 p.1).
When the power reaches the rail, the state of SEL1 is latched,
and this pin becomes REF, a buffer output of the signal applied
at Xin, typically 14.318MHz.
IOAPIC
SEL1/REF
4
VDD
VDD
VDD
I
OSC1 On-chip reference oscillator input pin. Requires either an
external parallel resonant crystal (nominally 14.318MHz) or
externally generated reference signal
XIN
5
O
On-chip reference oscillator pin. Drives an external parallel
resonant crystal. When an externally generated reference signal
is used at XIN, this pin remains unconnected.
This is a bi-directional pin (see app. note, p.6). At power up, it is
an input pin SEL3 for frequency selection (see table 1 p.1).
When the power reaches the rail, the state of SEL3 is latched,
and this pin becomes PCI clock output.
XOUT
12
I/O PD
SEL3/PCI0
13,14,17,18
VDD
O
3.3V PCI clock outputs. They are Synchronous to CPU clocks.
See fig.3, p. 4.
PCI(1:4)
8, 9, 10
26
VDD
VDD
O
3.3V Hub/AGP clock outputs. See fig.3 p.4.
3V66(0:2)
SEL2/USB
I/O PD
This is a bi-directional pin (see app. note, p.6). At power up, it is
an input pin SEL2 for frequency selection (see table 1 p.1).
When the power reaches the rail, the state of SEL2 is latched,
and this pin becomes a fixed 48MHz clock output for USB.
3.3V Fixed 48MHz DOT clock output
3.3V LVTTL input for frequency selection, see table 1 p.1. SEL0
also controls TS# functionality if TS# is 0 at power up. See fig.6
p.7.
27
19
VDD
VDD
O
I
DOT
SEL0
PU1
23
VDD
I
Serial data input pin. Conforms to the SMBus specification of a
Slave Receive/Transmit device. This pin is an input when
receiving data. It is an open drain output when acknowledging or
transmitting data. See SMBus function description, p. 8.
Serial clock input pin. Conforms to the SMBus specification.
This is a dual function input pin. During power up, if TS# is low, it
serves as a Tri-state control (TS#). Once high, this pin becomes
a Power Down control (PD#). See fig.6 p.7.
SDATA
22
28
VDD
VDD
I
I
SCLK
TS#/PD#
PU2
29,30,31,34,
35,36,37,40, 41
VDDS
O
O
3.3V SDRAM DIMM clock outputs. See table1, p.1 for frequency
selection. See fig.3, p.3 for timing relationship and SMBus
Byte3, Bit0.
2.5V Host clock outputs. See table1, p.1 for frequency selection.
3.3V Common Power Supply
2.5V Power Supply for CPU(0:1) and IOAPIC respectively.
Common Ground pins.
SDRAM
(0:8)
43,44
3,7,15,21,25
45, 48
1,6,11,16,20,24
, 32, 38, 42, 46
39,33
VDDC
CPU(0:1)
VDD
VDDC,VDDI
VSS
-
-
-
-
-
-
3.3V power support for SDRAM(0:8) clock output drivers.
VDDS
PU1 = Internal Pull-Up. Typical 250KΩ (range 200KΩ to 500KΩ). PD = Internal Pull-Down. Typical 50KΩ (range 25KΩ to 75KΩ)
PU2 = Internal Pull-Up Typical 50kΩ (range 25kΩ to 75kΩ)
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07070 Rev. **
5/4/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress
Page 2 of 21
CYPRESS [ CYPRESS ]
