欢迎访问ic37.com |
会员登录 免费注册
发布采购

C9926AY 参数 Datasheet PDF下载

C9926AY图片预览
型号: C9926AY
PDF下载: 下载PDF文件 查看货源
内容描述: [Processor Specific Clock Generator, CMOS, PDSO48, SSOP-40]
分类和应用: 时钟光电二极管外围集成电路晶体
文件页数/大小: 21 页 / 351 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号C9926AY的Datasheet PDF文件第4页浏览型号C9926AY的Datasheet PDF文件第5页浏览型号C9926AY的Datasheet PDF文件第6页浏览型号C9926AY的Datasheet PDF文件第7页浏览型号C9926AY的Datasheet PDF文件第9页浏览型号C9926AY的Datasheet PDF文件第10页浏览型号C9926AY的Datasheet PDF文件第11页浏览型号C9926AY的Datasheet PDF文件第12页  
PRELIMINARY  
C9926  
Low EMI Clock Generator for Intel 133MHz/ 2DIMM Chipset Systems  
2-Wire SMBus Control Interface  
The 2-wire control interface implements a read/write slave only interface according to SMBus specification. (See Fig. 7  
below). The device can read back by using standard SMBus command bytes. Sub addressing is not supported, thus all  
preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock  
output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported.  
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is  
high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the  
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer  
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer  
cycle is an 8-bit address. The LSB address Byte = 0 in write mode.  
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on  
the SDATA wire following reception of each byte. Data is transferred MSB first at a max rate of 100kbits/S. This device  
will also respond to a D3 address which sets it in a read mode. It will not respond to any other control interface  
conditions, and previously set control registers are retained.  
Transmit  
ACK  
ACK  
ACK  
ACK  
ACK  
Receive  
COMMAND BYTE  
(Don't Care)  
BYTE COUNT  
(Don't Care)  
BYTE 0  
(Valid)  
BYTE N  
(Valid)  
1
1
0
1
0
0
1
0
SDATA  
MSB  
LSB  
8
8
8
8
SCLK  
START CONDITION  
STOP CONDITION  
Fig.7a (WRITE)  
Transmit  
ACK BYTE COUNT  
BYTE 0  
(Valid)  
BYTE1  
(Valid)  
BYTE N  
(Valid)  
Receiv  
ACK  
ACK  
ACK  
ACK  
1
1
0
1
0
1
0
1
(Valid)  
SDATA  
MSB  
LSB  
8
8
8
8
SCLK  
START CONDITION  
STOP CONDITION  
Fig.7b (READ)  
Figure 7  
SMBus Communications Waveforms  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07070 Rev. **  
5/4/2001  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress  
Page 8 of 21  
 复制成功!