PRELIMINARY
C9926
Low EMI Clock Generator for Intel 133MHz/ 2DIMM Chipset Systems
IOAPIC Clock Synchronization and Phase Alignment
This device incorporates IOAPIC clock synchronization. With this feature, the IOAPIC clocks are derived from the CPU
clock. The IOAPIC clock lags the CPU clock by the specified 1.5ns to 3.5ns. Figure 3 shows the relationship between
the CPU and IOAPIC clocks.
Clock Phase Relationships
0ns
10ns
20ns
30ns
40ns
CPU CLOCK
CPU CLOCK
CPU CLOCK
66MHz
2.5ns
100MHz
133MHz
5ns
0ns
Sync
0ns
7.5ns
5ns
SDRAM CLOCK
SDRAM CLOCK
100MHz
133MHz
3.75ns
0ns
3.75ns
3V66 CLOCK
PCI CLOCK
66MHz
1.5ns~3.5ns
33MHz
IOAPIC CLOCK
33MHz
Fig.3
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress
Document#: 38-07070 Rev. **
5/4/2001
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