PRELIMINARY
C9926
Low EMI Clock Generator for Intel 133MHz/ 2DIMM Chipset Systems
Group Timing Relationships and Tolerances
CPU = 66.6MHz, SDRAM = 100MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM
CPU to 3V66
2.5
7.5
500
500
500
180 degrees phase shift
When rising edges line-up
3V66 leads
SDRAM to 3V66
3V66 to PCI
0
1.5-3.5
0
500
PCI to IOAPIC
1000
CPU = 100MHz, SDRAM = 100MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM
CPU to 3V66
5
500
500
500
500
1000
180 degrees phase shift
5
SDRAM to 3V66
3V66 to PCI
0
1.5-3.5
0
When rising edges line-up
3V66 leads
PCI to IOAPIC
CPU = 133.3MHz, SDRAM = 100MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM
CPU to 3V66
0
500
500
500
500
1000
When rising edges line-up
0
SDRAM to 3V66
3V66 to PCI
0
1.5-3.5
0
When rising edges line-up
3V66 leads
PCI to IOAPIC
CPU = 133.3MHz, SDRAM = 133.3MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM
CPU to 3V66
3.75
0
500
500
500
500
1000
180 degrees phase shift
SDRAM to 3V66
3V66 to PCI
3.75
1.5-3.5
0
3V66 leads
PCI to IOAPIC
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07070 Rev. **
5/4/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress
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