PRELIMINARY
CYW54907
15.4 LNLDO
Table 36. LNLDO Specifications
Specification
Notes
Min.
Typ.
Max.
Units
Input supply voltage, Vin
Min. VIN = VO + 0.15V = 1.35V (where VO = 1.2V)dropout
voltage requirement must be met under maximum load.
1.3
1.35
1.5
V
Output current
–
0.1
1.1
–
–
1.2
–
150
1.275
150
+4
mA
V
Output voltage, Vo
Dropout voltage
Programmable in 25 mV steps. Default = 1.2V.
At maximum load.
mV
Output voltage DC accuracy
Quiescent current
Includes line/load regulation.
No load.
–4
–
–
%
44
970
–
–
µA
Max. load.
–
990
5
µA
Line regulation
Load regulation
Leakage current
Output noise
V
in from (Vo + 0.1V) to 1.5V, 150 mA load.
Load from 1 mA to 150 mA.
Power-down.
–
mV/V
mV/mA
µA
–
0.02
–
0.05
10
–
@30 kHz, 60–150 mA load Co = 2.2 µF.
@100 kHz, 60–150 mA load Co = 2.2 µF.
–
–
60
35
nV/rt Hz
nV/rt Hz
PSRR
@ 1kHz, Input > 1.35V, Co= 2.2 µF,
Vo = 1.2V.
20
–
–
dB
LDO turn-on time
LDO turn-on time when the rest of the chip is up.
Total ESR (trace/capacitor): 5 mΩ–240 mΩ.
–
0.5a
–
140
2.2
1
180
4.7
2.2
µs
µF
µF
External output capacitor, Co
External input capacitor
Only use an external input capacitor at the LDO_VDD1P5
pin if it is not supplied from the CBUCK output.
Total ESR (trace/capacitor): 30 mΩ–200 mΩ.
a. Minimum capacitor value refe rs to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
Document Number: 002-19312 Rev. *C
Page 68 of 95
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