CYW43362
Table 10. CYW43362 During Reset and After Reset or During Sleep (Cont.)
During Reset
After Reset (and after firmware
initialization) or During Sleep
Signal Name/Group
I/O Type
Pull R
I/O
Pull R I/O
PUd
SPI_SDO
Digital
None
High Z
Output
SPI_CLK
SPI_CS
Digital
Digital
None
None
High Z
High Z
None
Input
Input
PUd
PUd
SPI_IRQ
Digital
None
High Z
Output
SDIO Signals
SDIO_CLK
SDIO_CMD
Digital
Digital
None
None
High Z
High Z
None
PUd
PUd
PUd
PUd
PUd
Input
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
SDIO_DATA0
SDIO_DATA1
SDIO_DATA2
SDIO_DATA3
Digital
Digital
Digital
Digital
None
None
None
None
High Z
High Z
High Z
High Z
Clock
PDe
Output (high)e, f
Input
XTAL_PU
Digital
Digital
CLK
PD
High Z
High Z
High Z
(CLK_REQ)
EXT_SLEEP_CLK
(external 32.768 kHz clock)
None
None
None
OSCIN
(reference clock)
None
Input
Bluetooth Coexistenceg
btcx_txconf
btcx_freq
Digital
Digital
Digital
Digital
None
None
None
None
High Z
High Z
High Z
High Z
Configurable
Configurable
Configurable
Configurable
Output
Input
Input
Input
btcx_rf_actvive
btcx_status
Document No. 002-14779 Rev. *G
Page 39 of 60
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