CYW43362
Table 9. WLBGA Signal Descriptions (Cont.)
Ball #
Signal Name
Type
Description
Power Supplies
B4
A5
WRF_ANA_VDD1P2
I
I
1.2V analog power supply
WRF_VCO_LDO_IN_
VDD1P8
1.4V to 1.8V VCO/LDO power supply input
B7
WRF_TCXO_VDD3P3
I
1.7V to 3.3V supply for the CYW43362 TCXO driver. To maintain a constant load
on the TCXO_IN pin, even when power is removed from the CYW43362,
connect this supply pin to a 1.7V to 3.3V supply that is present whenever the
external TCXO is powered up. Note that this should be a clean supply (do not
use VIO). If not used, this pin must be connected to ground.
C7
WRF_XTAL_VDD1P2
I
1.2V XTAL oscillator power supply. This supply is required for all clock options:
crystal, dedicated TCXO, and shared TCXO (WRF_TCXO_IN).
D1
D3
F7
WRF_PA_VDD
WRF_PADRV_VDD
WRF_AFE_VDD1P2
VDD
I
I
I
I
I
I
I
I
Internal power amplifier power supply (VBAT supported), high current
Internal power amplifier driver power supply (VBAT supported)
1.2V AFE power supply
H2, H3
G1
1.2V digital supply for the core
VDDIO_RF
RF I/O and OTP supply (3.3V)
H4
VDDIO
Digital I/O supply.
K5
VDDIO_SD
Digital I/O supply for SDIO interface signals.
1.2V analog supply to the internal LNA.
A3
WRF_LNA_VDD1P2
C5
WRF_VCO_LDO_
OUT_VDD1P2
O
VCO LDO output. Some designs may require a decoupling capacitor (nominal 0.22
µF) for optimal WLAN performance. Cypress recommends that a 0201 size footprint
for this capacitor be included in all designs in case the capacitor is necessary.
Ground
D4
WRF_ANA_GND
WRF_VCO_GND
WRF_PA_GND
WRF_XTAL_GND
WRF_PADRV_GND
VSS
–
–
–
–
–
–
Analog ground
A6
VCO ground
B2, D2
C6
Internal power amplifier ground
XTAL ground
E2
Internal power amplifier driver ground
Ground
E3, F3, F4,
G3, G4
E6
K2
L2
A4
WRF_AFE_GND
PMU_AVSS
–
–
–
–
AFE ground
PMU analog ground
SR_PVSS
Buck regulator: power switch ground
Internal Rx LNA ground
WRF_LNA_GND
No Connects
C4
WRF_GPIO_OUT
O
No Connect
Table 10. CYW43362 During Reset and After Reset or During Sleep
After Reset (and after firmware
initialization) or During Sleep
During Reset
Pull R I/O
Signal Name/Group
Reset/Control
I/O Type
Pull R
I/O
High Za, b
WL_RST_N
Digital
PD
PD
PD
Input
Input
Input
Input
Input
Input
PD c
PD c
EXT_SMPS_REQ
EXT_PWM_REQ
Digital
Digital
SPI Signals
PUd
SPI_SDI
Digital
None
High Z
Input
Document No. 002-14779 Rev. *G
Page 38 of 60
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