CYW43362
Table 9. WLBGA Signal Descriptions (Cont.)
Ball # Signal Name Type
Description
D7
OSCIN
I
XTAL oscillator amplifier input. This pin can also be used as the reference clock
input from a dedicated (that is, not shared) TCXO.
F6
XTAL_PU
O
External reference clock enable (Clock_Request)
Default mode (open source): XTAL_PU is driven HIGH when the clock is requested and pulled low with a weak internal
pull-down resistor when the clock is not requested.
Push-Pull: Always driven HIGH or LOW (no PU/PD). Push-Pull mode is enabled by software.
XTAL_PU internal pull-down (PD) resistances:
PD @ 1.8V (minimum, typical, maximum): 356 kΩ, 558 kΩ, 651 kΩ
PD @ 2.5V (minimum, typical, maximum): 356 kΩ, 559 kΩ, 652 kΩ
PD @ 3.3V (minimum, typical, maximum): 356 kΩ, 559 kΩ, 653 kΩ
XTAL_PU drive strength:
For 1.8V: 2.0 mA
For 2.5V: 5.0 mA
For 3.3V: 6.0 mA
Output slewing can be enabled or disabled by software; it is enabled by default.
J5
EXT_SLEEP_CLK
I
Input pin for optional high-precision 32.768 kHz Clock (Sleep Clock).
Document No. 002-14779 Rev. *G
Page 35 of 60
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