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BCM43362KUBG 参数 Datasheet PDF下载

BCM43362KUBG图片预览
型号: BCM43362KUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom Circuit, 1-Func, CMOS, PBGA69, WLBGA-69]
分类和应用: 电信电信集成电路
文件页数/大小: 60 页 / 5201 K
品牌: CYPRESS [ CYPRESS ]
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CYW43362  
Table 10. CYW43362 During Reset and After Reset or During Sleep (Cont.)  
During Reset  
After Reset (and after firmware  
initialization) or During Sleep  
Signal Name/Group  
I/O Type  
Pull R  
I/O  
Pull R I/O  
RF Switch Control  
rf_sw_ctl_0  
Digital  
PU  
PD  
PD  
PD  
High Z  
None  
None  
None  
None  
Output  
Output  
Output  
Output  
rf_sw_ctl_1  
rf_sw_ctl_2  
rf_sw_ctl_3  
Digital  
Digital  
Digital  
High Z  
High Z  
High Z  
GPIOsg  
gpio_x  
Digital  
None  
High Z  
Configurable  
Configurable  
a. Within 1.5 ms of WL_RST_N being driven high, the PMU changes this from PD to High-Z.  
b. Software can optionally enable a weak internal pull-down resistor.  
c. Internal pull-down resistor can be disabled via software.  
d. Software can optionally disable the weak internal pull-up for these signals.  
e. Default mode (Open source): XTAL_PU is driven HIGH when a clock is requested, and pulled low with a weak internal pull-down resistor when  
a clock is not requested.  
Push-Pull: Always driven HIGH or LOW (no PU/PD). Available via a strapping option for the FCFBGA and WLCSP packages.  
f.  
The clock is not requested during Sleep mode.  
g. The Bluetooth coexistence and GPIO signals have keepers that prevent them from floating when they aren’t connected; however, when they  
are connected to another component, prevention from floating can’t be assured by the keepers.  
9.2 WLAN GPIO Signals and Strapping Options  
The pins listed in Table 11 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few  
milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative  
function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor  
that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a  
10 kresistor or less.  
Note: Refer to the reference board schematics for more information.  
Table 11. GPIO Functions and Strapping Options  
Pin Name WLBGA Pin # Default  
Function  
Description  
GPIO_0  
E4  
0
spimode_sel  
This pin selects the host interface mode:  
0: SDIO  
1: gSPI  
Document No. 002-14779 Rev. *G  
Page 40 of 60  
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