CYW43362
Table 9. WLBGA Signal Descriptions (Cont.)
Ball # Signal Name Type
Description
SDIO Interface
F5
SDIO_DATA_2
I/O
SDIO data line 2. This pin has an internal weak pull-up resistor.
Note: By default, the internal pull-up is enabled, but it can be disabled
via software. The pull-up resistor is forced on for SPI mode since this
pin is unused in that mode.
L6
L5
SDIO_DATA_0/SPI_MISO
SDIO_DATA_1/SPI_IRQ
I/O
I/O
SDIO data line 0. This pin has an internal weak pull-up resistor.
Note: By default, the internal pull-up is enabled, but it can be disabled
via software.
SDIO data line 1. This pin has an internal weak pull-up resistor.
Note: By default, the internal pull-up is enabled, but it can be disabled
via software.
L7
SDIO_CLK/SPI_CLK
I
SDIO clock.
K6
SDIO_DATA_3/SPI_CSX
I/O
SDIO data line 3. This pin has an internal weak pull-up resistor.
Note: By default, the internal pull-up is enabled, but it can be disabled
by software.
K7
SDIO_CMD/SPI_MOSI
I/O
SDIO command line. This pin has an internal weak pull-up resistor.
Note: By default, the internal pull-up is enabled, but it can be disabled
by software.
SDIO/SPI weak internal pull-up resistances:
For 1.8V (minimum, typical, maximum): 34 kΩ, 51 kΩ, 86 kΩ
For 2.5V (minimum, typical, maximum): 21 kΩ, 32 kΩ, 54 kΩ
For 3.3V (minimum, typical, maximum): 16 kΩ, 24 kΩ, 37 kΩ
Software programmable SDIO/SPI drive strength options:
For 1.8V: 0.5 mA, 1.0 mA, 1.5 mA, 2.0 mA, 2.5 mA (default), and 3.0 mA
For 2.5V: 1.5 mA, 3.0 mA, 4.5 mA, 6.0 mA, 7.5 mA (default), and 9.0 mA
For 3.3V: 2.0 mA, 4.0 mA, 6.0 mA, 8.0 mA, 10.0 mA (default), and 12.0 mA
JTAG Interface
G6
G5
H6
JTAG_TMS
JTAG_TDO
JTAG_TDI
I
For normal operation, connect as described in the JTAG specification (IEEE Std
1149.1). Otherwise, if JTAG is not used, this pin can be left unconnected (NC)
as it has an internal weak pull-up resistor.
O
I
For normal operation, connect as described in the JTAG specification (IEEE Std
1149.1). Otherwise, if JTAG is not used, this pin can be left unconnected (NC).
This pin is also muxed with UART_TX, which can be enabled by software.
For normal operation, connect as described in the JTAG specification (IEEE Std
1149.1). Otherwise, if JTAG is not used, this pin can be left unconnected (NC)
as it has an internal weak pull-up resistor. This pin is also muxed with
UART_RX, which can be enabled by software.
H7
G7
JTAG_TCK
I
I
For normal operation, connect as described in the JTAG specification (IEEE Std
1149.1). Otherwise, if JTAG is not used, this pin can be left unconnected (NC)
as it has an internal weak pull-up resistor.
JTAG_TRST_L
For normal operation, connect as described in the JTAG specification (IEEE Std
1149.1). Otherwise, if JTAG is not used, this pin can be left unconnected (NC)
as it has an internal weak pull-up resistor.
JTAG drive strength:
For 1.8V: 1.0 mA
For 2.5V: 2.5 mA
For 3.3V: 3.0 mA
Output slewing can be enabled or disabled by software; it is enabled by default.
Clocks
A7
D6
WRF_TCXO_IN
I
Reference clock input for use when sharing a TCXO with another chip, such as
a BT/FM/GPS chip (see Frequency References on page 10). This input has an
internal DC blocking capacitor, so do not include an external DC blocking
capacitor. Connect directly to the external TCXO. This input pad is powered by
the WRF_TCXO_VDD3P3 supply, which should be continually powered
whenever the external TCXO is powered, even when the CYW43362 is in reset,
thereby ensuring this input maintains a constant load on the TCXO signal in all
device modes. If unused, ground this pin.
OSCOUT
O
XTAL oscillator amplifier output. See Frequency References on page 10.
Document No. 002-14779 Rev. *G
Page 34 of 60
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