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BCM43362KUBG 参数 Datasheet PDF下载

BCM43362KUBG图片预览
型号: BCM43362KUBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Telecom Circuit, 1-Func, CMOS, PBGA69, WLBGA-69]
分类和应用: 电信电信集成电路
文件页数/大小: 60 页 / 5201 K
品牌: CYPRESS [ CYPRESS ]
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CYW43362  
8. WLAN Software Architecture  
8.1 Host Software Architecture  
The host driver (DHD) provides a transparent connection between the host operating system and the CYW43362 media (for exam-  
ple, WLAN) by presenting a network driver interface to the host operating system and communicating with the CYW43362 over an  
interface-specific bus (SPI, SDIO, and so on) to:  
Forward transmit and receive frames between the host network stack and the CYW43362 device, and  
Pass control requests from the host to the CYW43362 device, returning the CYW43362 device responses  
The driver communicates with the CYW43362 over the bus using a control channel and a data channel to pass control messages  
and data messages. The actual message format is based on the BDC protocol.  
8.2 Device Software Architecture  
The wireless device, protocol, and bus drivers are run on the embedded ARM® processor using a Cypress-defined operating sys-  
tem called HNDRTE, which transfers data over a propriety Cypress format over the SDIO/SPI interface between the host and device  
(BDC/LMAC). The data portion of the format consists of IEEE 802.11 frames wrapped in a Cypress encapsulation. The host side  
architecture provides all missing functionality between a network device and the Cypress device interface. The host can also be cus-  
tomized to provide functionality between the Cypress device interface and a full network device interface.  
This transfer requires a message-oriented (framed) interconnect between the host and device. The SDIO bus is an addressed bus—  
each host-initiated bus operation contains an explicit device target address—and does not natively support a higher-level data frame  
concept. Cypress has implemented a hardware/software message encapsulation scheme that ignores the bus operation code  
address and prefixes each frame with a 4-byte length tag for framing. The device presents a packet-level interface over which data,  
control, and asynchronous event (from the device) packets are supported.  
The data and control packets received from the bus are initially processed by the bus driver and then passed on to the protocol  
driver. If the packets are data packets, they are transferred to the wireless device driver (and out through its medium), and a data  
packet received from the device medium follows the same path in the reverse direction. If the packets are control packets, the proto-  
col header is decoded by the protocol driver. If the packets are wireless IOCTL packets, the IOCTL API of the wireless driver is  
called to configure the wireless device. The microcode running in the D11 core processes all time-critical tasks.  
8.2.1 Remote Downloader  
When the CYW43362 powers up, the DHD initializes and downloads the firmware to run in the device.  
Figure 21. WLAN Software Architecture  
DHD Host Driver  
SPI/SDIO  
BDC/LMAC Protocol  
Wireless Device Driver  
D11 Core  
Document No. 002-14779 Rev. *G  
Page 31 of 60  
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