CYW43362
are baseband filter calibration for optimum transmit and receive performance and LOFT calibration for leakage reduction. In addition,
I/Q Calibration, R Calibration, and VCO Calibration are performed on-chip.
7. CPU and Global Functions
7.1 WLAN CPU and Memory Subsystem
The CYW43362 includes an integrated ARM Cortex™-M3 processor with internal RAM and ROM. The ARM Cortex-M3 processor is
a low-power processor that features low gate count, low interrupt latency, and low-cost debugging. It is intended for deeply embed-
ded applications that require fast interrupt response features. The processor implements the ARM® architecture v7-M with support
for Thumb®-2 instruction set. ARM Cortex-M3 delivers 30% more performance gain over ARM7TDMI.
At 0.19 µW/MHz, the Cortex-M3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit
devices on MIPS/µW. It supports integrated sleep modes.
ARM Cortex-M3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced
silicon area. ARM Cortex-M3 supports independent buses for Code and Data access (ICode/DCode and System buses). ARM Cor-
tex-M3 supports extensive debug features including real time trace of program execution.
On-chip memory for the CPU includes 240 KB SRAM and 448 KB ROM.
7.2 One-Time Programmable Memory
Various hardware configuration parameters may be stored in an internal 1024-bit One-Time Programmable (OTP) memory, which is
read by system software after device reset. In addition, customer-specific parameters, including the system vendor ID and the MAC
address, can be stored, depending on the specific board design.
The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0.
The entire OTP array can be programmed in a single write cycle using a utility provided with the Cypress WLAN manufacturing test
tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state
can be altered during each programming cycle.
Prior to OTP programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the ref-
erence board design package. Documentation on the OTP development process is available on the Cypress customer support por-
tal.
7.3 GPIO Interface
Five general purpose I/O (GPIO) pins are available on the CYW43362 that can be used to connect to various external devices.
GPIOs are tristated by default. Subsequently, they can be programmed to be either input or output pins via the GPIO control register.
They can also be programmed to have internal pull-up or pull-down resistors.
GPIO_0 is initially used as a strapping option to select between SDIO and SPI modes.
GPIOs 3, 4, and 5 are multiplexed with the Bluetooth Coexistence Interface. By default, these pins are BT_COEX pins. Software can
reprogram these pins to behave as GPIOs.
GPIO_1 is a GPIO by default, but can be reprogrammed by software to become the BTCX_FREQ signal.
7.4 JTAG Interface
The CYW43362 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing
during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and character-
ization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test
points or a header on all PCB designs.
7.5 UART Interface
One UART interface can be enabled by software as an alternate function on the JTAG pins. UART_RX is available on the JTAG_TDI
pin, and UART_TX is available on the JTAG_TDO pin.
The UART is primarily for debugging during development. By adding an external RS-232 transceiver, this UART enables the
CYW43362 to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It
is compatible with the industry standard 16550 UART, and it provides a FIFO size of 64 × 8 in each direction.
Document No. 002-14779 Rev. *G
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