CX82100 Home Network Processor Data Sheet
6.3
Supported Configurations
Table 6-4 lists supported SDRAM configurations. There are only one or two memory ICs
at most that reside on the external SDRAM bus (e.g., two 2M x 8 SDRAMs are required
to get 4 MB). This bus is not shared with any other external function. Since the EMC
buffers write data phases, this pipelined activity implies that the SDRAM bus can be busy
concurrently with asynchronous and independent host bus transfers. (An external host can
read/write SDRAM as well.)
Table 6-4. Allowed SDRAM Configurations
Total
Memory
Config.
No. of
SDRAM
Config.
SDRAM
SDRAM
No. of
SDRAM
No. of
Rows
SDRAM
No. of
Memory
SDRAMs
Capacity
Banks
Columns
2 MB
4 MB
8 MB
1Mb x 16
2Mb x 16
4Mb x 16
1
2
1
1Mb x 16
2Mb x 8
4Mb x 16
16 Mb
16 Mb
64 Mb
2
2
4
2Kb
2Kb
4Kb
256
512
256
6.4
Access Cycles
The EMC’s SDRAM 16-bit interface is synchronous. All of the SDRAM inputs are
registered on the positive edge of MCLK. The SDRAM uses an internal pipelined
architecture to achieve high-speed operation. Read and write accesses to the SDRAM are
burst oriented (it's been noted from the simulation that the EMAC design only allows
read accesses to the SDRAM to be burst oriented). A burst of 8 allows a cache line (16
bytes) to be refilled in one single read. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or WRITE command.
6.5
6.6
Initialization
The SDRAM requires a 200 µs delay prior to applying an executable command. The
delay begins after reset when power and clock are stable. The microcontroller should not
access the SDRAM during this time, otherwise all processes will be held up while the
EMC inserts wait states for the full initialization duration. No user intervention is
required during the initialization process. All appropriate settings are managed by the
SDRAM controller.
Refresh
The SDRAM controller supports Auto-Refresh. Refresh requests are generated to meet a
15.625 µs per row interval (to be safe, it is preferable that refresh requests could be
generated at a rate less than 15.625 µs per row interval). Refresh cycles are transparent to
the host, but will insert wait cycles if the memory is accessed during a refresh request.
Refresh requests have top priority when accessing the memory. Refresh cycles will not
interrupt a memory cycle in process.
6-4
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