CX82100 Home Network Processor Data Sheet
6.10
EMC I/O Clock Interface and Timing
The EMC I/O clock interface is illustrated in Figure 6-2.
The EMC I/O timing is illustrated in Figure 6-3.
Figure 6-2. EMC Clocking Interface
scan mux
CLKGEN
MODULE
BCLK
MCLK
MCLK
BCLK
PAD
scan mux
MA
MA
Q
D
PAD
PAD
scan mux
MD
MD
D
Q
asb_sdram
ext_sdram
HNP
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Figure 6-3. EMC I/O Timing
BCLK
C
F
MCLK
MD
D
E
DATA
A
B
ADDR
MA
Notes:
Where:
A = tck-q
B = tasu
C = clock skew
D = ta
+
tdsm
+
tpo
tck-q = asb_sdram flop clk-q delay
tsu = asb_sdram flop setup time
th = asb_sdram flop hold time
tdsm = HNP scan mux delay
tpo = output pad delay
=
tdi + tdsm + tpo
E = tsu
+ tpi + tdsm
F = (clk period / 2) - tdi - tdsm - tpo
tpi = input pad delay
tdi = HNP inverter delay
ta = sdram read access time
101545_027
6-6
Conexant Proprietary and Confidential Information
101306C
CONEXANT [ CONEXANT SYSTEMS, INC ]
