CX82100 Home Network Processor Data Sheet
6.11
SRAM Interface
The HNP EMC can alternatively interface to SRAM memory. The SDRAM associated
pins are used for this interface and are multiplexed to either interface to SDRAM or
SRAM. SDRAM or SRAM interface is controlled by the EMCR register and allows for
different external sizes and up to two SRAM devices. Using two 512-kbyte SRAM
devices (256k x 16 each), a maximum of 1 MB of external SRAM can be achieved. The
EMCR register controls for SRAM read/write wait state control, selection of one or two
memory chips, and selection of various sizes for each of the memories.
The SDRAM-to-SRAM signal mapping is shown in Table 6-6.
If one SRAMs are used, connect CE_SRAM1# to the SRAM CE# (Chip Enable) and
leave CE_SRAM2# open.
If two SRAMs are used, connect CE_SRAM1# to the lower address range SRAM
(SRAM 1) CE# and CE_SRAM2# to the upper address range SRAM (SRAM 2) CE#.
For the SRAMs, connect OE# (Output Enable), BLE# (Byte Low Enable), and BHE#
(Byte High Enable) to VSS.
Table 6-6. HNP to SDRAM/SRAM Interface Signal Mapping
HNP Pin Signal
SDRAM Interface
SRAM Pin Signal
MCKE
CKE
A17
A16
A15
A14
A13
A12
MCAS#
MB1
MCAS#
MB1
MB0
MM1
MM0
MB0
MM1
MM0
MA[11:0]
MD[15:0]
MCS#
MRAS#
MWE#
A[11:0]
D[15:0]
CS#
RAS#
WE#
A[11:0]
IO[15:0]
CE# (SRAM 1)
CE# (SRAM 2)
WE#
101306C
Conexant Proprietary and Confidential Information
6-7
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