CX82100 Home Network Processor Data Sheet
Table 6-1. EMC SDRAM Interface Signal Descriptions
Pin Name
MD[15:0]
MA[11:0]
MB[1:0]
MM[1:0]
MRAS#
MCAS#
I/O
I/O
O
O
O
O
O
Signal Name
Memory Data
Memory Address
Bank Address
Memory Mask
Row Address Strobe
Description
Bi-directional data access bus for DRAM.
Multiplexed row and column address for access of data up to 8 MB.
Selects active memory bank.
Input mask signal for write accesses.
Starts SDRAM access with strobe of row address.
Strobes column address and data bytes.
Column Address
Strobe
MWE#
MCS#
MCKE
MCLK
O
O
O
O
Memory Write Enable
Memory Chip Select
Memory Clock Enable Memory Clock activation.
Memory Clock All SDRAM signals sampled on positive edge.
Indicates write access to SDRAM.
Enables the SDRAM command decoder.
Table 6-2. PC100 Compliant Mode Register
Bit No.
11:7
6:4
Name
Supported Function
Reserved.
CAS# Latency.
011 =
LTMODE
3 cycles.
All Other =
Wrap Type.
0 = Linear.
Reserved.
3
WT
BL
1 = Interleave.
2:0
Burst Length.
011 =
8 cycles.
Reserved.
All Other =
The SDRAM clock runs at 100 MHz, however, 125 MHz rated SDRAM is required in
order to guarantee setup time margin.
6-2
Conexant Proprietary and Confidential Information
101306C
CONEXANT [ CONEXANT SYSTEMS, INC ]
