CX82100 Home Network Processor Data Sheet
5.3.10
Host Master Mode Peripheral Handshake (MSTR_HANDSHAKE: 0x002D0024)
(CX82100-41/-42)
Bit(s)
31:5
4
Type
Default
Name
Description
Reserved.
RW
1’b0
Mstr_handshake4
HCS4 HRDY# Handshake Enable.
0 = Disable HRDY# handshake.
1 = Enable HRDY# handshake.
Reserved.
3:1
0
RW
1’b0
Mstr_handshake0
HRDY# Polarity.
0 = Active low
1 = Active high
5.3.11
Host Master Mode DMA Source Address (HDMA_SRC_ADDR: 0x002D0028)
Bit(s)
31:24
23:0
Type
Default
Name
Description
Reserved.
RW
24’b0
HDma_source_addr
Least significant 24 bits of the address of the first byte of DMA source
data.
5.3.12
Host Master Mode DMA Destination Address (HDMA_DST_ADDR: 0x002D002C)
Bit(s)
31:24
23:0
Type
Default
Name
Description
Reserved.
Least significant 24 bits of the first location of the DMA destination.
RW
24’b0
HDma_dest_addr
5.3.13
Host Master Mode DMA Byte Count (HDMA_BCNT: 0x002D0030)
Bit(s)
31:22
21:0
Type
Default
Name
Description
Reserved.
The number of bytes of data to be transferred via the host DMA.
RW
22’b0
HDma_byte_count
5.3.14
Host Master Mode DMA Timers (HDMA_TIMERS: 0x002D0034)
Bit(s)
31:16
15:8
Type
Default
Name
Description
Reserved.
RW
RW
8’b0
8’b0
HDMA_ISOC_TIMER
Timer which dictates the transfer rate for an isochronous mode
DMA transfer in terms of the number of BCLK periods.
7:0
HDMA_INACTIVE_TIMER
The minimum interval, in terms of number of BCLK periods,
between subsequent accesses to an external DMA source or
destination.
5-16
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