CX82100 Home Network Processor Data Sheet
6.12
EMC Register
The EMC register is identified in Table 6-7.
Table 6-7. EMC Register
Register Label
EMCR
Register Name
External Memory Control Register
ASB Address
0x00350010
Type
RW
Default Value
0x00000000
Ref.
6.12.1
6.12.1
External Memory Control Register (EMCR: 0x00350010)
Bit(s)
7:6
Type
RW
Default
Name
SRWSC
Description
SRAM Read/Write Wait State Control.
00 = No extra delay.
2’b00
01 = Delayed by one BCLK period.
10 = Delayed by two BCLK periods.
11 = Delayed by three BCLK periods.
Note: The delay cycles are extra to the normal access cycles.
SRAM Chip Select 2.
5:4
RW
2’b00
SRCSEL2
00 = Do not select the second SRAM chip.
01 = Select the second SRAM chip, size = 64K x 16.
10 = Select the second SRAM chip, size = 128K x 16.
11 = Select the second SRAM chip, size = 256K x 16.
Notes:
1. EXMSEL must be 2’b10 if the second SRAM chip is selected.
2. The size for the second SRAM must be no greater than the size
of the first SRAM.
3. If the second SRAM size is programmed at a value greater than
that of the first SRAM, then the actual size for the second SRAM
will be reduced to the same size as the first automatically by the
hardware.
3:2
1:0
RW
RW
2’b00
2’b00
SRCSEL1
EXMSEL
SRAM Chip Select 1.
00 = Do not select the first SRAM chip.
01 = Select the first SRAM chip, size = 64K x 16.
10 = Select the first SRAM chip, size = 128K x 16.
11 = Select the first SRAM chip, size = 256K x 16.
Note: EXMSEL must be 2’b10 if the first SRAM chip is selected.
External Memory Select.
00 = Select SDRAM interface; SDRAM in Disabled Mode.
01 = Select SDRAM interface; SDRAM in Enabled Mode.
10 = Select SRAM interface.
11 = Reserved.
6-8
Conexant Proprietary and Confidential Information
101306C
CONEXANT [ CONEXANT SYSTEMS, INC ]
