CX82100 Home Network Processor Data Sheet
6.7
Read
Write
No acceleration is provided for read accesses. Multiple memory banks allow multiple
rows to be active simultaneously. This reduces the need for precharge and activate cycles,
allowing a faster aggregate throughput.
6.8
6.9
A 2-dword buffer is provided to speed up random and DMA write accesses.
Throughput
Better than 114 MB/s for 16-byte cache-line fills and 177 MB/s for buffered 16-byte
writes. Random read or write single accesses operate at 50 MB/s and 200 MB/s,
respectively. Table 6-5 summarizes the throughput for each access type.
Table 6-5. SDRAM Throughput
16-bit SDRAM Interface
32-bit Access
No. of BCLK Cycles
1 dword
4 dwords (Seq Burst)
Write
Read
2
9
8
14
Write immediately following Write
Read immediately following Read
16-bit Access
Write
Read
Write immediately following Write
Read immediately following Read
2
12
1 word
15
18
4 words (Seq Burst)
2
7
2
8
10
11
12
12
101306C
Conexant Proprietary and Confidential Information
6-5
CONEXANT [ CONEXANT SYSTEMS, INC ]
