CX82100 Home Network Processor Data Sheet
6
External Memory Controller Interface Description
6.1
PC100 Compliant SDRAM Interface
The External Memory Controller (EMC) provides a 16-bit interface to support up to 8
MB of external SDRAM. Figure 6-1 shows a typical SDRAM functional block diagram.
Note that the actual SDRAM design varies from vendor to vendor. Figure 6-1 also shows
an Intel PC100 compliant interface between the EMC and the SDRAM. Table 6-1 lists
the definition for each interface signal. A PC100 compliant SDRAM must also support a
mode register whose functions are defined in Table 6-2. The mode register is
programmable through the MRS (Mode Register Set) command defined in the PC100
Specification (see Reference [6]).
Figure 6-1. SDRAM Interface
SDRAM
MM[1:0]
Data I/O +
Control
MD[15:0]
Logic
MB[1:0]
RA
Banks
(2x or 4x)
Decode +
Control
Logic
MA[11:0]
External
Memory
Controller
ASB
CA
Decode +
Control
Logic
MRAS#
MCAS#
MW E#
MCS#
Control Logic
Command
Refresh
Bank
MCKE
MCLK
Mode register
HNP
101545_025
101306C
Conexant Proprietary and Confidential Information
6-1
CONEXANT [ CONEXANT SYSTEMS, INC ]
