CX82100 Home Network Processor Data Sheet
5.3.2
Host Master Mode Read-Wait-State Control Register (HST_RWST: 0x002D0004)
Bit(s)
31:25
24:20
Type
Default
Name
Description
Reserved.
RW
5’b00111
HST_RWS4
HCS4 Wait State Control for Master Mode Read Cycles.
Length of read cycle = count value * 1 BCLK period + 1 BCLK period.
Reserved.
HCS0 Wait State Control for Master Mode Read Cycles.
Length of read cycle = count value * 1 BCLK period + 1 BCLK period.
19:5
4:0
RW
5’b00111
HST_RWS0
5.3.3
Host Master Mode Write-Wait-State Control Register) (HST_WWST: 0x002D0008)
Bit(s)
31:25
24:20
Type
Default
Name
Description
Reserved.
RW
5’b00111
HST_WWS4
HCS4 Wait State Control for Master Mode Write Cycles.
Length of read cycle = count value * 1 BCLK period + 1 BCLK period.
Reserved.
HCS0 Wait State Control for Master Mode Write Cycles.
Length of read cycle = count value * 1 BCLK period + 1 BCLK period.
19:5
4:0
RW
5’b00111
HST_WWS0
5.3.4
Host Master Mode Transfer Control Register (HST_XFER_CNTL: 0x002D000C)
Bit(s)
31:8
7
Type
Default
Name
Description
Reserved.
RW
1’b0
Hcs4_ds_polarity
HCS4 External Data Strobe Polarity.
0 = Negative data strobe polarity.
1 = Positive data strobe polarity.
Reserved.
HCS4 External Transfer Mode.
0 = WE# and RE# transfer mode.
1 = R/W# and DS# transfer mode.
Reserved.
6:4
3
RW
1’b0
Hcs4_xfer_mode
2:0
5.3.5
Host Master Mode Read Control Register 1 (HST_READ_CNTL1: 0x002D0010)
Bit(s)
31:28
Type
RW
Default
4’b0
Name
HRcs4_Tcss
Description
HCS4 Chip Select Setup Time Relative to RE# or R/W#.
Length = count value * 1 BCLK period.
Reserved.
HCS4 Chip Select Hold Time Relative to RE# or R/W#.
Length = count value * 1 BCLK period.
Reserved.
27:16
15:12
RW
4’b0
HRcs4_Tcsh
11:0
5-14
Conexant Proprietary and Confidential Information
101306C
CONEXANT [ CONEXANT SYSTEMS, INC ]
