CX82100 Home Network Processor Data Sheet
5.3.6
Host Master Mode Read Control Register 2 (HST_READ_CNTL2: 0x002D0014)
Bit(s)
31:28
Type
RW
Default
4’b0
Name
HRcs4_Tas
Description
HCS4 Address Setup Time to Active Read.
Length = count value * 1 BCLK period + 1 BCLK period.
Reserved.
HCS4 and HCS5 Address Hold Time Following Active Read.
Length ≥ count value * 1 BCLK period + 4 BCLK periods.
Reserved.
27:16
15:12
RW
4’b0
HRcs4_Tah
11:0
5.3.7
Host Master Mode Write Control Register 1 (HST_WRITE_CNTL1: 0x002D0018)
Bit(s)
31:28
Type
RW
Default
4’b0
Name
HWcs4_Tcss
Description
HCS4 Chip Select Setup Time Relative to WE# or R/W#.
Length = count value * 1 BCLK period.
Reserved.
HCS4 Chip Select Hold Time Relative to WE# or R/W#.
Length = count value * 1 BCLK period.
Reserved.
27:16
15:12
RW
4’b0
HWcs4_Tcsh
11:0
5.3.8
Host Master Mode Write Control Register 2 (HST_WRITE_CNTL2: 0x002D001C)
Bit(s)
31:28
Type
RW
Default
4’b0
Name
HRcs4_Tas
Description
HCS4 Address Setup Time to Active Write.
Length = count value * 1 BCLK period + 1 BCLK period.
Reserved.
HCS4 Address and Data Hold Time Following Active Write.
For data, Length = count value * 1 BCLK period + 1 BCLK period.
For address, Length ≥ count value * 1 BCLK period + 5 BCLK periods.
Reserved.
27:16
15:12
RW
4’b0
HRcs4_Tadh
11:0
5.3.9
Host Master Mode Peripheral Size (MSTR_INTF_WIDTH: 0x002D0020)
Bit(s)
31:5
4
Type
Default
Name
Description
Reserved.
RW
1’b0
Mstr_intf_width4
HCS4 Data Length.
0 = 16-bit data length.
1 = 8-bit data length.
Reserved.
3:0
101306C
Conexant Proprietary and Confidential Information
5-15