CX82100 Home Network Processor Data Sheet
5.3
Host Master Mode Registers
5.3.1
Host Control Register (HST_CTRL: 0x002D0000)
Bit(s)
31:12
11
Type
Default
Name
Description
Reserved.
R/W
1'b0
DMA_SRC_ADDR_INC_DISABLE
Disable DMA Source Address Increment.
0 = Enable DMA Source Address Increment.
1 = Disable DMA Source Address Increment.
Disable DMA Destination Address Increment.
0 = Enable DMA Destination Address Increment.
1 = Disable DMA Destination Address Increment.
Host Master Mode DMA Transfer Mode Select.
00 = Asynchronous DMA Mode.
10
R/W
RW
1'b0
DMA_DST_ADDR_INC_DISABLE
HDMA_MODE_SEL
9:8
2’b00
01 = Reserved.
10 = Isochronous DMA Mode using internal timer.
11 = Reserved.
Reserved.
Enable the arbiter to lock 940 ADR/SEQ/ and Bursts.
0 = Disable arbiter to lock 940 ADR/SEQ/ and Bursts.
1 = Enable arbiter to lock 940 ADR/SEQ/ and Bursts.
Reserved.
7
6
RW
RW
1’b0
1’b0
EN_BLOCK_ARM
RUN_MAP
5
4
Run-Time Memory Map.
0 = Flash ROM @ starting address 0x00000000,
internal RAM @ starting address 0x00180000.
1 = Internal RAM @ starting address 0x00000000,
Flash ROM @ starting address 0x00180000.
3:2
1:0
RW
RW
2’b10
2’b00
XDM_SZ
External Dynamic Memory Size.
00 = 2 MB.
01 = 4 MB.
10 = 8 MB.
11 = Reserved.
HST_HIRQ
HIRQ0# Output State for External Host.
0x = Off.
10 = Asserted low.
11 = De-asserted and pulled high.
101306C
Conexant Proprietary and Confidential Information
5-13
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