CX82100 Home Network Processor Data Sheet
5.1.5
Host Master Mode Timing (CX82100-11/-12/-51/-52)
Host Master Mode Read Operation (Accessing an External Device)
The Host Master Mode read timing is illustrated in Figure 5-3 and listed in Table 5-3.
•
•
•
HRD# and HWR# signals are used when the appropriate bit of the Host Master
Mode Transfer Control Register is low.
HR/W# and HDS# signals are used when the appropriate bit of Host Master Mode
Transfer Control Register is high.
Tpw is programmable via the Host Master Mode Read Wait-State Control registers
(HST_RWST).
Host Master Mode Write Operation (Accessing an External Device)
The Host Master Mode write timing is illustrated in Figure 5-4 and listed in Table 5-4.
•
•
•
HRD# and HWR# signals are used when the appropriate bit of the Host Master
Mode Transfer Control Register is low.
HR/W# and HDS# signals are used when the appropriate bit of Host Master Mode
Transfer Control Register is high.
Tpw is programmable via the Host Master Mode Write Wait-State Control registers
(HST_WWST).
101306C
Conexant Proprietary and Confidential Information
5-5
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