CX82100 Home Network Processor Data Sheet
5
Host Interface Description
The Host Interface operates in Master Mode which allows the HNP to access external
Flash ROM and an optional slave device.
The host interface master mode operates asynchronously and is not referenced to any host
clock input or output.
5.1
Master Mode
5.1.1
Host Master Mode Interface Signals
The Host Master Mode consists of a 21-bit output address bus, 16-bit bidirectional data
bus, read enable output, write enable output, Flash ROM chip enable output, Spare chip
enable output, and Spare interrupt request input.
In master mode, the host interface is selected to drive the host control/address/data
interface when the host ASB slave DSEL is active.
Host Master Mode signals are illustrated in Figure 5-1 and listed in Table 5-1.
Figure 5-1. Host Master Mode Signals
FLASH ROM
HAD[29:16], HC[7:1]
21
16
A[20:0]
D[15:0]
WR#
HAD[15:0]
HWR#
Host Interface
HRD#
RD#
HAD[29:16], HC[7:1]
21
16
HAD[29:16], HC[7:1]
HAD[15:0]
HC09
HCS0#
CE#
HAD[15:0]
HWR#
Spare
HRD#
(UART Example)
HC08
HC[3:1]
HAD[7:0]
HWR#
3
8
HCS0#
HCS4#
HIRQ4#
A[3:1]
HC00
D[7:0]
WRUA#
RDUA#
CE#
HAD31
GPIO25
HRD#
HCS4#
HIRQ4#
HNP
IRQ#
101306_016
101306C
Conexant Proprietary and Confidential Information
5-1
CONEXANT [ CONEXANT SYSTEMS, INC ]
