CX82100 Home Network Processor Data Sheet
Figure 5-3. Waveforms for Host Master Mode Read Operation (CX82100-11/-12/-51/-52)
address
HA[21:1]
HD[15:0]
HCS[X]#
HRD#
data
HW R#
HR/W #
HDS#
Tas
Tcss
Tah
Tds
Tcsh
Tpw
Tdh
100603_017
Table 5-3. Timing for Host Master Mode Read Operation Based on a 100 MHz BCLK (CX82100-11/-12/-51/-52)
Symbol
Tas
Tpw
Tds
Parameter
Programmable address setup to active read
Programmable read pulse width
Min.
10
10
5
Max.
160
320
—
Units
ns
ns
Required data setup to end of active read
ns
Tdh
Tah
Tcsh
Tcss
Required data hold time following active read
Programmable address hold time following active read
Programmable chip select hold time relative to RE# or R/W#
Programmable chip select setup time relative to RE# or R/W#
40
40
0
240
90
150
150
ns
ns
ns
ns
0
5-6
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