CX82100 Home Network Processor Data Sheet
HRDY# Description (CX82100-41/-42)
HRDY# is used to extend a Host Interface operation. The use of HRDY# can be enabled
or disabled by setting or clearing the corresponding HRDY# Handshake Enable bit in the
MSTR_HANDSHAKE register (0x002D0024).
When HRDY# is enabled, the polarity of HRDY# can be programmed by setting or
clearing bit 0 of the MSTR_HANDSHAKE register.
•
With HRDY# Polarity low (default polarity, bit 0 of 0x002D0024 = 0), HRDY# low
indicates the target on the Host Bus is ready/waiting and HRDY# high indicates the
target is busy. In this case, chip selects HCS0#-HCS5# will assert when HRDY# is
low and will not assert when HRDY# is high.
•
With HRDY# Polarity high (bit 0 of 0x002D0024 = 1), HRDY# high indicates the
target on the Host Bus is ready/waiting and HRDY# low indicates the target is busy.
In this case, chip selects HCS0#-HCS5# will assert when HRDY# is high and will
not assert when HRDY# is low.
When HRDY# is enabled, the pulse widths of HRD# and HWR# are controlled by either
the HRDY# signal or the timing specified by the Host Read/Write Wait State Control
Register, whichever has longer cycle time. HRD# and HWR# will never have a smaller
width than the programmed values thus minimum Host Interface cycle time is
guaranteed.
When HRDY# is disabled, the state of HRDY# is ignored and the timing of the host
interface control and data signals are controlled by the timing configuration registers:
HST_RWST, HST_WWST, HST_READ_CNTL1, HST_READ_CNTL2,
HST_WRITE_CNTL1, and HST_WRITE_CNTRL2.
101306C
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