CX82100 Home Network Processor Data Sheet
Table 5-2. Chip Select Address Ranges
HCS Signal
HCS0# (HC00)
HCS4# (HAD31)
Typical Slave Device
Flash ROM
Application dependent
ASB Address Range
Size
4 MB
0x00400000–0x007FFFFF
0x002C0000–0x002CFFFF 64 KB
5.1.2
Flash Memory Interface
The master mode host interface addresses up to 32 Mbit (2 M x 16) of Flash ROM using
HA[21:1]. HCS0# is designed specifically to select Flash ROM. Flash ROM can be
optionally used for the HNP executable memory instead of internal ROM. Typically, a 32
Mbit (2 M x 16) Flash ROM such as an Intel TE28F320C3BA90 or equivalent, or a 16
Mbit (1 M x 16) Flash ROM such as an Intel TE28F160C3BA90 or equivalent, is used.
The HNP supports only 16-bit Flash memories, therefore, all writes to a 16-bit Flash must
be word transfers.
Refer to Section 3.4 for a description of booting from Flash ROM.
5.1.3
Interfacing to Other Slave Devices
The peripheral interface is completely programmable via the Host Control Registers.
These registers allow programming of parameters such as peripheral bus width (8-bit or
16-bit), timing for both read and write operations, and control signal polarity.
During a transfer with an 8-bit peripheral, bit 0 of the address, which is omitted when
interfacing to a 16-bit peripheral, is issued on HD15. (This pin is available in 8-bit mode
because the data bus is using only bits HD[7:0].)
During a transfer with a 16-bit peripheral, there are two byte-write enables (one for the
lower 8 bits of the transfer and another for the upper 8 bits), which allow for individual
byte writes to 16-bit peripherals which support such transfers. The high-byte write enable
is assigned to pin HAD29 and the low-byte write enable is assigned to pin HC09. When
writing data to a 16-bit device which does not support multiple byte write enables, the
host must ensure that writes to the device are initiated internally as either word or dword
transfers.
5.1.4
Host Master Mode DMA Engine
Both asynchronous and isochronous modes of operation are available and are selected by
the MSb (bit 9) of the HDMA_MODE_SEL field in the HST_CTRL register.
Asynchronous DMA Transfer Mode
In Asynchronous DMA Transfer Mode, data transfers complete as fast as the source and
destination bus environments allow.
Isochronous DMA Transfer Mode
In Isochronous DMA Transfer Mode, the data is transferred to or from the external
peripheral at a specified rate.
The user supplies the isochronous transfer rate using an internal timer, as selected by the
HDMA_MODE_SEL field in the HST_CTRL register. This rate can be programmed by
the HDMA_ISOC_TIMER field in the HDMA_TIMERS register.
101306C
Conexant Proprietary and Confidential Information
5-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
