CX82100 Home Network Processor Data Sheet
Figure 5-4. Waveforms for Host Master Mode Write Operation (CX82100-11/-12/-51/-52)
address
HA[21:1]
HD[15:0]
HCS[X]#
HRD#
data
HW R#
HR/W#
HDS#
Tas
Tcss
Tadh
Tpw
Tcsh
101603_018
Table 5-4. Timing for Host Master Mode Write Operation Based on a 100 MHz BCLK (CX82100-11/-12/-51/-52)
Symbol
Tas
Tpw
Parameter
Programmable address setup to active write
Programmable read pulse width
Programmable address and data hold time following active write (address
hold time is longer that data hold time so min. and max. is based on the
address hold time).
Min.
10
10
Max.
160
320
200
Units
ns
ns
Tadh
50
ns
Tcsh
Tcss
Programmable chip select hold time relative to WE# or R/W#
Programmable chip select setup time relative to WE# or R/W#
0
0
150
150
ns
ns
101306C
Conexant Proprietary and Confidential Information
5-7