CX82100 Home Network Processor Data Sheet
5.1.6
Host Master Mode Timing (CX82100-41/-42)
Host Master Mode Read Operation (Accessing an External Device)
The Host Master Mode read timing is illustrated in Figure 5-5 and listed in Table 5-5.
•
•
•
•
HRD# and HWR# signals are used when the appropriate bit of the Host Master
Mode Transfer Control Register is low.
HR/W# and HDS# signals are used when the appropriate bit of Host Master Mode
Transfer Control Register is high.
Tpw is programmable via the Host Master Mode Read Wait-State Control registers
(HST_RWST).
HRDY# is used for handshaking when the appropriate bit of the Host Master Mode
Peripheral Handshake register is set.
Host Master Mode Write Operation (Accessing an External Device)
The Host Master Mode write timing is illustrated in Figure 5-6 and listed in Table 5-6.
•
•
•
•
HRD# and HWR# signals are used when the appropriate bit of the Host Master
Mode Transfer Control Register is low.
HR/W# and HDS# signals are used when the appropriate bit of Host Master Mode
Transfer Control Register is high.
Tpw is programmable via the Host Master Mode Write Wait-State Control registers
(HST_WWST).
HRDY# is used for handshaking when the appropriate bit of the Host Master Mode
Peripheral Handshake register is set.
5-8
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