CX82100 Home Network Processor Data Sheet
Table 5-1. Host Master Mode Signals
Pin Signal
Host Master
Pin No.
Signal
Signal Name
Host Bus Data [15:0]
Mode Signal
Direction
HAD[15:0]
HD[15:0]
HA[20:7]
N7, M9, L8, K9, J9, N10,
P10, M10, L9, K10, L10,
M11, J10, L11, N12, P12
I/O
HAD[29:16]
L3, L1, M2, M1, N2, N1, M3,
O
Host Bus Address [20:7]
N3, P3, M4, N4, P4, L4, M5
HC[07:01]
HC08 (HRD#)
HC09 (HWR#)
HC10 (HRDY#)
HC00 (HCS0#)/GPIO32*
HA[6:0]
HRD#
HWR#
HRDY#
HCS0#
L5, M6, K6, N6, P6, L6, P7
M13
M12
P14 (CX82100-41/-42)
P14 (CX82100-11/-51/-52)
P13 (CX82100-41/-42)
J8
O
O
O
I
Host Bus Address [6:0]
Host Bus Read Enable
Host Bus Write Enable
Handshake for slow peripherals
Host Chip Select 0 (Flash ROM)
O
HAD31 (HCS4#)/GPIO31*
HCS4#
O
Host Chip Select 4 (Spare)
Notes:
* = These pins default to host functions; they can be reconfigured to GPIO pins.
The HNP Host Master Mode supports only the little-endian mode data byte orientation.
As depicted in Figure 5-2, the 32-bit little-endian ASB data bus BD[31:0] is mapped
to/from the 16-bit external host data bus HD[15:0] according to the even/odd half-word
(16 bits) data address alignment indicated by the address bit HA1.
Figure 5-2. Little-Endian Mode Data Bus Mapping
BD[31:0] to/from ASB
BD[31:0] to/from ASB
31:24
23:16
15:8
15:8
7:0
7:0
31:24
23:16
15:8
15:8
7:0
7:0
BD
BD
HD
HD
even half-word address: HA1 = 0
odd half-word address: HA1 = 1
101545_15
The ASB side may address the host as a slave in 16-bit or 32-bit mode. The 32-bit mode
accesses are converted to two external 16-bit accesses. The host interface is allocated 5
MB total address space. This address space is allocated to the six chip selects HCS[5:0]#
as shown in Figure 5-1 and Table 5-2.
5-2
Conexant Proprietary and Confidential Information
101306C
CONEXANT [ CONEXANT SYSTEMS, INC ]
