CX82100 Home Network Processor Data Sheet
9.3.14
GPIO Interrupt Enable Register 1 for GPIO[15:14; 8:5] (GPIO_IER1: 0x003500E4)
GPIO_IER1 is the interrupt input enable register for GPIO[15:14; 8:5].
Note: If an interrupt input is enabled for GPIO[X], then GPIO[X] must be configured
as an input.
Bit(s)
31:16;
31≥Y≥16,
Y = Bit #
Type
RO
Default
Name
Description
GPIO[X] Interrupt Enable Mask, 15≥X≥0.
See specific GPIO_IEMSK{X},
bit
15≥X≥0,
X = Y-16.
Reading:
Return 0.
Writing:
0 = Mask off the function associated with GPIO_IE{X}.
1 = Enable the function associated with GPIO_IE{X}.
GPIO[X] Interrupt Enable, 15≥X≥0.
Reading:
15:0;
15≥Y≥0,
Y = Bit #
RW
See specific GPIO_IE{X},
bit
15≥X≥0,
X = Y.
Return the last value written to bit #Y.
Writing:
0 = Disable the GPIO[X] interrupt if GPIO_IEMSK{X} = 1; don't
care, otherwise.
1 = Enable the GPIO[X] interrupt if GPIO_IEMSK{X} = 1; don't
care, otherwise.
Bit(s)
31
30
29:25
24
23
22
21
20:16
15
14
13:9
8
7
6
5
Type
RO
RO
Default
1’b0
1’b0
Name
GPIO_IEMSK15
GPIO_IEMSK14
Description
GPIO15 Interrupt Enable Mask.
GPIO14 Interrupt Enable Mask.
Reserved.
GPIO8 Interrupt Enable Mask.
GPIO7 Interrupt Enable Mask.
GPIO6 Interrupt Enable Mask.
GPIO5 Interrupt Enable Mask.
Reserved.
GPIO15 Interrupt Enable.
GPIO14 Interrupt Enable.
Reserved.
GPIO8 Interrupt Enable.
GPIO7 Interrupt Enable.
GPIO6 Interrupt Enable.
GPIO5 Interrupt Enable.
Reserved.
RO
RO
RO
RO
1’b0
1’b0
1’b0
1’b0
GPIO_IEMSK8
GPIO_IEMSK7
GPIO_IEMSK6
GPIO_IEMSK5
RW
RW
1’b0
1’b0
GPIO_IE15
GPIO_IE14
RW
RW
RW
RW
1’b0
1’b0
1’b0
1’b0
GPIO_IE8
GPIO_IE7
GPIO_IE6
GPIO_IE5
4:0
101306C
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