CX82100 Home Network Processor Data Sheet
9.3.13
GPIO Interrupt Status Register 3 for GPIO[39:37; 32] (GPIO_ISR3: 0x003500E0)
GPIO_ISR3 is the interrupt input status register for GPIO[39:37; 32].
Note: If an interrupt is level-sensitive, the corresponding status bit will remain a 1 as
long as the interrupt source is not removed. The status bit can be cleared only
after the interrupt source is removed and a 1 is written to the bit.
Bit(s)
7:0;
7≥Y≥0,
Y = Bit #
Type
RR
Default
Name
Description
GPIO[X] Interrupt Status, 39≥X≥32.
See specific GPIO_IS{X},
bit
39≥X≥32,
X = Y+32.
Reading:
bit #Y = 0 = > No interrupt detected on GPIO[X].
bit #Y = 1 = > Interrupt input detected on GPIO[X].
Writing:
0 to bit #Y = > no effect
1 to bit #Y = > clear the interrupt on GPIO[X].
Note: If the interrupt is level-sensitive, the status bit will remain a 1 as
long as the interrupt resource is not removed. The bit can be cleared
only after the resource is removed and a 1 is written to it.
Bit(s)
31:8
7
6
5
4:1
0
Type
Default
Name
Description
Reserved.
GPIO39 Interrupt Status.
GPIO38 Interrupt Status.
GPIO37 Interrupt Status.
Reserved.
RR
RR
RR
1’b0
1’b0
1’b0
GPIO_IS39
GPIO_IS38
GPIO_IS37
RR
1’b0
GPIO_IS32
GPIO32 Interrupt Status.
9-12
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