1.0 Product Description
CX28394/28395/28398
1.2 Pin Assignments
Quad/x16/Octal—T1/E1/J1 Framers
Figure 1-12. CX28395 Logic Diagram (Multiplexed System Bus Mode)
Hardware Reset
System Clock
I
I
I
RST*
Microprocessor
Interface and
Control
SYSCKI
MCLK
Processor Clock
(MPU)
Synchronous Bus Mode
Motorola Bus Mode
Address Strobe
I
I
I
I
I
SYNCMD
MOTO*
AS* (ALE*)
CS1*
DTACK*
INTR1*
O
O
Data Transfer Acknowledge
Interrupt Request 1
Chip Select 1
Chip Select 2
CS2*
INTR2*
ONESEC1
ONESEC2
O
Interrupt Request 2
Data or Read Strobe
I
I
DS* (RD*)
R/W* (W*)
AD[7:0]
PIO One-Second Timer 1
PIO One-Second Timer 2
Read/Write or Write Strobe
Data or Multiplexed I/O
Address/Data Bus
Address Bus
I
A[11:0]
Transmitter
(XMTR)
TCKO[16:1]
O
O
Transmit Clock Out
Transmit Clock In
1544 KHz All Ones Clock
2048 KHz All Ones Clock
I
I
I
TCKI[16:1]
T1ACKI
TNRZO[16:1]
Transmit Positive / Transmit NRZ Out
E1ACKI
Receiver
(RCVR)
Receive Clock In
Receive NRZ In
I
I
RCKI[16:1]
RNRZ[16:1]
Transmit System Bus
(TSB)
TINDO[A:D]
TFSYNC[A:D]
TMSYNC[16:1]
O
Bused Timeslot Indicator
Bused TSB Clock In
Bused TSB PCM Data In
TSB Signalling In
I
I
I
TSBCKI[A:D]
TPCMI[A:D]
TSIGI[16:1]
PIO Bused TSB Frame Sync
PIO TSB Multiframe Sync
Receive System Bus
(RSB)
RPCMO[A:D]
O
O
Bused RSB PCM Data Out
Bused Timeslot Indicator
Bused RSB Clock In
I
RSBCKI[A:D]
RINDO[A:D]
RFSYNC[A:D]
RMSYNC[16:1]
RSIGO[16:1]
PIO Bused RSB Frame Sync
PIO RSB Multiframe Sync
O
RSB Signalling
Test Clock In
Test Mode Select
Test Data In 1
I
I
I
TCK
TMS
TDI1
Boundary Scan
(JTAG)
TDO1
TDO2
O
O
Test Data Out 1
Test Data Out 2
Test Data In 2
Test Reset In
I
I
TDI2
TRST*
I = Input, O = Output
PIO = Programmable I/O; controls located at PIO (address 018)
1-30
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
