CX28394/28395/28398
1.0 Product Description
Quad/x16/Octal—T1/E1/J1 Framers
1.2 Pin Assignments
Figure 1-11. CX28395 Logic Diagram (Non-Multiplexed System Bus Mode)
Microprocessor Interface
and Control
Hardware Reset
System Clock
I
I
I
I
I
I
RST*
(MPU)
SYSCKI
MCLK
Processor Clock
Synchronous Bus mode
Motorola Bus mode
Address Strobe
SYNCMD
MOTO*
AS*(ALE*)
O
O
Data Transfer Acknowledge
Interrupt Request
DTACK*
INTR*
Chip Select 1
Chip Select 2
PIO One-Second Timer
I
I
CS1*
CS2*
ONESEC
Data or Read Strobe
Read/Write or Write Strobe
DS*(RD*)
R/W*(W*)
AD[7:0]
I
I
Data or Multiplexed
Address/Data Bus
Address Bus
I/O
I
A[11:0]
Transmitter
(XMTR)
Transmit Clock In
1544 KHz All Ones Clock
2048 KHz All Ones Clock
I
I
I
TCKI[16:1]
T1ACKI
TCKO[16:1]
TNRZO[16:1]
O
O
Transmit Clock Out
Transmit Transmit NRZ Out
E1ACKI
Receiver
(RCVR)
RCKI[16:1]
RNRZ[16:1]
RNEGI[16:1]
Receive Clock In
Receive NRZ In
Receive Negative In
I
I
I
Transmit System Bus
(TSB)
TSB Clock In
TSBCKI[16:1]
I
TFSYNC[16:1]/TMSYNC[16:1]
TSB Frame/Multiframe Sync
PIO
TSB PCM Data In
TSB Signalling In/
TPCMI[16:1]
TSIGI[16:1]
I
I
Receive System Bus
(RSB)
O
RSB PCM Data Out
RPCMO[16:1]
RSB Clock In
I
RSBCKI[16:1]
RFSYNC[16:1]/RMSYNC[16:1]
RSIGO[16:1]
PIO RSB Frame/Multiframe Sync
O
RSB Signalling
Boundary Scan
(JTAG)
Test Clock In
Test mode Select
Test Data In 1
Test Data In 2
Test Reset In
I
I
I
I
I
TCK
TMS
TDI1
TDI2
TRST*
Test Data Out 1
Test Data Out 2
O
O
TDO1
TDO2
I= Input, O= Output
PIO = Programmable I/O; controls located at PIO (address 018)
100054E
Conexant
1-29
CONEXANT [ CONEXANT SYSTEMS, INC ]
