1.0 Product Description
CX28394/28395/28398
1.2 Pin Assignments
Quad/x16/Octal—T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (2 of 9)
Pin Label
Signal Name
Device (1)
Microprocessor Interface (MPU) (Continued)
I/O
Definition
CS*
Chip Select
4, 8
I
Active-low enables read/write decoder. Active high ends
current read or write cycle and places data bus output in
high impedance.
DS*(RD*)
Data Strobe or
Read Strobe
4, 5, 8
4, 5, 8
I
I
Active-low read data strobe (RD*) for MOTO* = 1, or
data strobe (DS*) for MOTO* = 0.
R/W*(WR*)
Read/Write
Direction or
Write Strobe
Active-low write data strobe (WR*) for MOTO* = 1, or
data select (R/W*) for MOTO* = 0.
ONESEC
One Second
Timer
4, 8
PIO
PIO
Controls or marks one-second interval used for status
reporting. When input, the timer is aligned to ONESEC
rising edge. When output, rising edge indicates start of
each one-second interval.
ONESEC1
ONESEC2
One Second
Timer
5
Controls or marks one-second interval used for status
reporting. When input, the timer is aligned to ONESEC
rising edge. When output, rising edge indicates start of
each one-second interval. ONESEC1 is the one second
timer for framers 1 to 8, ONESEC2 is the one second
timer for framers 9 to 16.
INTR*
Interrupt
Request
4, 8
O
O
Open drain active low output signifies one or more
pending interrupt requests. INTR* goes to
high-impedance state with weak (>50 kΩ) internal pullup
resistance after processor has serviced all pending
interrupt requests.
INTR1*
INTR2*
Interrupt
Request
5
Open drain active low output signifies one or more
pending interrupt requests. INTRn* goes to
high-impedance state with weak (>50kΩ) internal pullup
resistance after processor has serviced all pending
interrupt requests. INTR1* is the interrupt request for
framers 1 to 8, INTR2* is the interrupt request for
framers 9 to 16.
DTACK*
Data Transfer
Acknowledge
4, 8
5
O
O
Open drain active low output signifies in-progress data
transfer cycle. DTACK* remains asserted (low) for as
long as AS* and CS* are both active-low.
DTACK1*
DTACK2*
Data Transfer
Acknowledge
Open drain active low output signifies in-progress data
transfer cycle. DTACKn* remains asserted (low) for as
long as AS* and CSn* are both active-low.
1-32
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
