1.0 Product Description
CX28394/28395/28398
1.2 Pin Assignments
Quad/x16/Octal—T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (4 of 9)
Pin Label
Signal Name
Device (1)
Transmitter (XMTR) (Continued)
I/O
Definition
TCKO[4:1]
TCKO[8:1]
TCKO[16:1]
TX Clock Output
4
8
5
O
O
O
Line rate clock. TCKO equals selected TCKI or T1ACKI
(E1ACKI).
TNRZO[4:1]
TNRZO[8:1]
TNRZO[16:1]
TX Non Return
to Zero Data
4
8
5
Line-rate data output from transmitter on rising edge of
TCKO. TNRZO does not include ZCS encoded bipolar
violations.
MSYNCO[4:1]
MSYNCO[8:1]
MSYNCO[16:1]
TX Multiframe
Sync
4
8
5
Active high for one TCKI clock cycle to mark the first bit
of TX multiframe coincident with TNRZO. Output on
rising edge of TCKO.
Receiver (RCVR)
RCKI[4:1]
RCKI[8:1]
RCKI[16:1]
RX Clock Input
4
8
5
I
I
I
Line rate clock samples RPOSI and RNEGI or RNRZ.
RNRZI[4:1]
RNRZI[8:1]
RNRZI[16:1]
RX Positive Rail
Input
4
8
5
Line rate data input on rising edge of RCKI. Non-return
to zero (NRZ) receive data.
RPOSI[4:1]
RPOSI[8:1]
RX Positive Rail
Input
4
8
Line rate data input on rising edge of RCKI. RPOSI and
RNEGI levels are interpreted as received AMI pulses,
encoded as follows:
RPOSI RNEGI
RX Pulse Polarity
No pulse
Negative AMI pulse
Positive AMI pulse
Invalid (decoded as a pulse)
0
0
1
1
0
1
0
1
Unipolar. Non-return to zero (NRZ) data may be
connected to RPOSI or RNEGI in which case the other
input should be connected to ground. In this
configuration RAMI [RCR0; addr 040] should be set to 1
(receive AMI line format) and DIS_LCV
[RALM; addr 045] should be set to 1 (disable LCV
counting and reporting).
RNEGI[4:1]
RNEGI[8:1]
RX Negative Rail
Input
4
8
I
Line rate data input on rising edge of RCKI. See RPOSI
signal definition.
RDLO[4:1]
RDLO[8:1]
RX Data Link
Output
4
8
O
Line rate NRZ data output from receiver on falling edge
of RCKI. All receive data is represented at the RDLO pin.
However, selective RDLO bit positions are also marked
by RDLCKO for external data link applications.
RDLCKO[4:1]
RDLCKO[8:1]
RX Data Link
Clock Output
4
8
O
Gapped version of RCKI for external data link
applications. RDLCKO high clock pulse coincides with
low RCKO pulse interval during selected time slot bits,
otherwise RDLCKO is low (see Figure 2-4, Receive
External Data Link Waveforms).
1-34
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
