CX28394/28395/28398
1.0 Product Description
Quad/x16/Octal—T1/E1/J1 Framers
1.2 Pin Assignments
Table 1-6. Hardware Signal Definitions (1 of 9)
Pin Label
Signal Name
Device (1)
Microprocessor Interface (MPU)
I/O
Definition
RST*
Hardware Reset
4, 5, 8
I
High-to-low-to-high cycle forces registers to their
power-up state and all PIO pins to the input state. RST*
is not mandatory since power-on reset circuit performs
an identical function. RST* must remain asserted for a
minimum of 2 processor clock cycles (MCLK or SYSCKI,
depending on SYNCMD selection).
SYSCKI
MCLK
System Clock
4, 5, 8
4, 5, 8
I
I
Required 32.768 MHz clock for internal use. Supplied
from external source.
Processor Clock
System applies MCLK in the range of 8–36 MHz for use
with synchronous MPU applications. MCLK is used
when SYNCMD = 1 and ignored when SYNCMD = 0.
SYNCMD
Sync mode
4, 5, 8
I
Selects synchronous or asynchronous read/write timing
with respect to MCLK. Supports Intel- or Motorola-style
buses:
0 = Asynchronous Bus; read and write latches are
asynchronously controlled by CS*, DS*, and R/W*
signals.
1 = Synchronous Bus; MCLK rising edge samples
CS*, DS*, and R/W* to determine valid read/write cycle
timing.
MOTO*
Motorola Bus
Mode
4, 5, 8
I
Selects Intel- or Motorola-style microprocessor
interface. DS*, R/W*, A[11:0], and AD[7:0] functions are
affected.
0 = Motorola; AD[7:0] is data, A[11:0] is address,
DS* is data strobe, and R/W* indicates read (high) or
write (low) data direction.
1 = Intel; AD[7:0] is multiplexed address/data, A[7:0]
is ignored, A[11:8] is address, DS* is read strobe (RD*),
and R/W* is write strobe (WR*).
A[10:0]
A[11:0]
Address Bus
Address Bus
4
I
I
Address used to identify a register for subsequent
read/write data transfer cycle. In Motorola bus mode, all
eleven address bits (A[10:0]) are valid. In Intel bus
mode, only upper three bits (A[10:8]) are used.
5, 8
Address used to identify a register for subsequent
read/write data transfer cycle. In Motorola bus mode, all
twelve address bits (A[11:0]) are valid. In Intel bus
mode, only upper four bits (A[11:8]) are used.
AD[7:0]
Data Bus or
Address Data
4, 5, 8
4, 5, 8
I/O
I
Multiplexed address/data (Intel) or data only(Motorola).
Refer to MOTO* signal definition.
AS*(ALE)
Address Strobe
For all processor bus modes, AS* falling edge
asynchronously latches address from A[11:0]
(Motorola) or A[11:8], AD[7:0] (Intel) to identify one
register for subsequent read/write data transfer cycle.
CS1*, CS2*
Chip Select
5
I
Active-low enables read/write decoder. Active high ends
current read or write cycle and places data bus output in
high impedance. CS1* is the chip select pin for framers
1 to 8, CS2* is the chip select for framers 9 to 16.
100054E
Conexant
1-31
CONEXANT [ CONEXANT SYSTEMS, INC ]
