1.0 Product Description
CX28394/28395/28398
1.2 Pin Assignments
Quad/x16/Octal—T1/E1/J1 Framers
Figure 1-8. CX28394 Logic Diagram (Multiplexed System Bus Mode)
Microprocessor Interface
and Control
Hardware Reset
System Clock
I
RST*
(MPU)
I
I
SYSCKI
MCLK
Processor Clock
Synchronous Bus mode
Motorola Bus mode
Address Strobe
I
SYNCMD
MOTO*
AS*(ALE*)
CS*
O
Data Transfer Acknowledge
Interrupt Request
I
I
DTACK*
INTR*
O
Chip Select
PIO One-Second Timer
I
ONESEC
Data or Read Strobe
Read/Write or Write Strobe
I
I
DS*(RD*)
R/W*(W*)
AD[7:0]
Data or Multiplexed
Address/Data Bus
I/O
Address Bus
I
A[10:0]
LIU Serial
Port Interface
(SERIO)
O
Serial Clock Out
SERCKO
SERDO
SERCS*
Serial Data In
I
SERDI
O
O
Serial Data Out
Serial Port Chip Select
Transmitter
(XMTR)
Transmit Clock In
1544 KHz All Ones Clock
2048 KHz All Ones Clock
I
I
I
TCKI[4:1]
T1ACKI
E1ACKI
TCKO[4:1]
O
Transmit Clock Out
TPOSO[8:1]/TNRZO[4:1]
TNEGO[8:1]/MSYNCO[4:1]
O
O
Transmit Positive/Transmit NRZ Out
Transmit Negative/Transmit
Multiframe Sync Out
Receiver
(RCVR)
RCKI[4:1]
RPOSI[4:1]
RNEGI[4:1]
Receive Clock In
Receive Positive In
Receive Negative In
I
I
I
Transmit System Bus
(TSB)
Bused TSB Clock In
TSBCKI[A]
TPCMI[A]
TSIGI[4:1]
TDLI[4:1]
I
TINDO[A]
TFSYNC[A]
O
Bused Time Slot Indicator
Bused TSB PCM Data In
TSB Signalling In/
I
I
I
PIO Bused TSB Frame Sync
TMSYNC[4:1]
TDLCKO[4:1]
TSB MUltiframe Sync
Transmit Datalink Clock Out
PIO
O
Transmit Datalink Data In
Receive System Bus
(RSB)
O
Bused RSB PCM Data Out
RPCMO[A]
RINDO[A]
Bused RSB Clock In
I
RSBCKI[8:1]
O
PIO
PIO
PIO
O
Bused Time Slot Indicator
Bused RSB Frame Sync
RSB Multiframe Sync
RSB Signalling
Receive Datalink Clock Out
Receive Datalink Data Out
Signalling Freeze
RFSYNC[A]
RMSYNC[4:1]
RSIGO[4:1]
RDLCKO[4:1]
RDLO[4:1]
O
O
SIGFRZ[4:1]
Boundary Scan
(JTAG)
Test Clock In
Test mode Select
Test Data In
I
I
I
I
TCK
TMS
TDI
Test Data Out
O
TDO
Test Reset In
TRST*
I= Input, O= Output
PIO = Programmable I/O; controls located at PIO (address 018)
1-26
Conexant
100054E
CONEXANT [ CONEXANT SYSTEMS, INC ]
