CX28394/28395/28398
1.0 Product Description
Quad/x16/Octal—T1/E1/J1 Framers
1.2 Pin Assignments
Figure 1-9. CX28398 Logic Diagram (Non-Multiplexed System Bus Mode)
Microprocessor Interface
and Control
Hardware Reset
System Clock
I
RST*
(MPU)
I
I
SYSCKI
MCLK
Processor Clock
Synchronous Bus mode
Motorola Bus mode
Address Strobe
I
SYNCMD
MOTO*
AS*(ALE*)
CS*
O
O
Data Transfer Acknowledge
Interrupt Request
I
I
DTACK*
INTR*
Chip Select
PIO One-Second Timer
I
ONESEC
Data or Read Strobe
Read/Write or Write Strobe
I
I
DS*(RD*)
R/W*(W*)
AD[7:0]
Data or Multiplexed
Address/Data Bus
I/O
Address Bus
I
A[11:0]
LIU Serial
Port Interface
(SERIO)
O
Serial Clock Out
SERCKO
SERDO
SERCS*[2:1]
Serial Data In
I
SERDI
O
O
Serial Data Out
Serial Port Chip Select
Transmitter
(XMTR)
Transmit Clock In
1544 KHz All Ones Clock
2048 KHz All Ones Clock
I
I
I
TCKI[8:1]
T1ACKI
E1ACKI
TCKO[8:1]
O
Transmit Clock Out
TPOSO[8:1]/TNRZO[8:1]
TNEGO[8:1]/MSYNCO[8:1]
O
O
Transmit Positive/Transmit NRZ Out
Transmit Negative/Transmit
Multiframe Sync Out
Receiver
(RCVR)
RCKI[8:1]
RPOSI[8:1]
RNEGI[8:1]
Receive Clock In
Receive Positive In
Receive Negative In
I
I
I
Transmit System Bus
(TSB)
TSB Clock In
TSBCKI[8:1]
TPCMI[8:1]
I
TFSYNC[8:1]/TMSYNC[8:1]
TINDO[8:1]/TDLCKO[8:1]
PIO TSB Frame/Multiframe Sync
TSB PCM Data In
I
I
O
Time Slot Indicator/Transmit
Datalink Clock Out
TSB Signalling In/
TSIGI[8:1]/TDLI[8:1]
Transmit Datalink Data In
Receive System Bus
(RSB)
O
RSB PCM Data Out
RPCMO[8:1]
RFSYNC[8:1]/RMSYNC[8:1]
RINDO[8:1]/RDLCKO[8:1]
PIO RSB Frame/Multiframe Sync
RSB Clock In
I
RSBCKI[8:1]
O
Time Slot Indicator/Receive
Datalink Clock Out
RSIGO[8:1]/RDLO[8:1]
SIGFRZ[8:1]
O
RSB Signalling/Receive
Datalink Data Out
PIO Signalling Freeze
Boundary Scan
(JTAG)
Test Clock In
Test mode Select
Test Data In
I
I
I
I
TCK
TMS
TDI
Test Data Out
O
TDO
Test Reset In
TRST*
I= Input, O= Output
PIO = Programmable I/O; controls located at PIO (address 018)
100054E
Conexant
1-27
CONEXANT [ CONEXANT SYSTEMS, INC ]
