CX28394/28395/28398
1.0 Product Description
Quad/x16/Octal—T1/E1/J1 Framers
1.2 Pin Assignments
Table 1-6. Hardware Signal Definitions (3 of 9)
Pin Label
Signal Name
Device (1)
LIU Serial Interface
I/O
Definition
SERDI
Serial Data Input
4, 8
I
Serial data input from an LIU is sampled on rising edge
of SERCKO and written into Serial Data Register; addr
023.
SERCKO
Serial Clock
4, 8
O
Serial bit clock provided for transmitting and receiving
serial LIU data on SERDI and SERDO. SERCKO
frequency is 1.024 MHz or 8.192 MHz selectable.
SERDO
SERCS*
Serial Data
Output
4, 8
4
O
O
Address and data is output to an LIU serially on SERDO.
Data changes on falling edge of SERCKO.
Serial Chip
Select
Chip select line used to select an LIU’s serial port for
communication. SERCS is controlled in Serial
Configuration Register; addr 025.
SERCS1*
SERCS2*
Serial Chip
Selects
8
O
Chip select lines used to select an LIU’s serial port for
communication. SERCS1* and SERCS2* are
independently controlled in Serial Configuration
Register; addr 025.
Transmitter (XMTR)
TCKI[4:1]
TCKI[8:1]
TCKI[16:1]
TX Clock Input
4
8
5
I
Primary TX line rate clocks for transmitter signals:
TPOSO, TNEGO, TNRZO, MSYNCO, TDLI, and TDLCKO.
If TSLIP is bypassed, TCKI also clocks TSB signals.
T1ACKI
T1 All Ones
Clock
4, 5, 8
I
System optionally applies T1ACKI to use for T1 AIS
transmission in case the selected primary transmit clock
source fails. T1ACKI is either manually or automatically
switched to replace TCKI (see [AISCLK; addr 075]).
Systems without a T1 AIS clock should tie T1ACKI to
ground.
E1ACKI
E1 All Ones
Clock
4, 5, 8
I
System optionally applies E1ACKI to use for E1 AIS
transmission in case the selected primary transmit clock
source fails. E1ACKI is either manually or automatically
switched to replace TCKI (see [AISCLK; addr 075]).
Systems without an E1 AIS clock should tie E1ACKI to
ground.
TPOSO[4:1]
TPOSO[8:1]
TX Positive Rail
Output
4
8
O
O
I
Line rate data output from ZCS encoder changes on
rising edge of TCKO. Active-high marks transmission of
a positive AMI pulse.
TNEGO[4:1]
TNEGO[8:1]
TX Negative Rail
Output
4
8
Line-rate data output from ZCS encoder changes on
rising edge of TCKO. Active high marks transmission of a
negative AMI pulse.
TDLI[4:1]
TDLI[8:1]
TX Data Link
Input
4
8
Selected time slot bits are sampled on TDLCKO falling
edge for insertion into the transmit output stream during
external data link applications.
TDLCKO[4:1]
TDLCKO[8:1]
TX Data Link
Clock
4
8
O
Gapped version of TCKI for external data link
applications. TDLCKO high clock pulse coincides with
low TCKI pulse interval during selected time slot bits,
else TDLCKO low (see [DL3_TS; addr 015]).
100054E
Conexant
1-33
CONEXANT [ CONEXANT SYSTEMS, INC ]
