CX28394/28395/28398
1.0 Product Description
Quad/x16/Octal—T1/E1/J1 Framers
1.2 Pin Assignments
Figure 1-7. CX28394 Logic Diagram (Non-Multiplexed System Bus Mode)
Microprocessor Interface
and Control
Hardware Reset
System Clock
I
RST*
(MPU)
I
SYSCKI
MCLK
Processor Clock
I
Synchronous Bus mode
Motorola Bus mode
Address Strobe
I
SYNCMD
MOTO*
AS*(ALE*)
CS*
O
O
Data Transfer Acknowledge
Interrupt Request
DTACK*
INTR*
I
I
ONESEC
Chip Select
PIO One-Second Timer
I
Data or Read Strobe
Read/Write or Write Strobe
I
I
DS*(RD*)
R/W*(W*)
AD[7:0]
Data or Multiplexed
Address/Data Bus
I/O
Address Bus
I
A[10:0]
LIU Serial
Port Interface
(SERIO)
SERCKO
SERDO
SERCS*
O
Serial Clock Out
Serial Data In
O
O
Serial Data Out
I
SERDI
Serial Port Chip Select
Transmitter
(XMTR)
TCKO{4:1]
Transmit Clock In
1544 KHz All Ones Clock
2048 KHz All Ones Clock
I
I
I
TCKI[4:1]
T1ACKI
E1ACKI
O
Transmit Clock Out
TPOSO[4:1]/TNRZO[4:1]
TNEGO[4:1]/MSYNCO[4:1]
O
O
Transmit Positive/Transmit NRZ Out
Transmit Negative/Transmit
Multiframe Sync Out
Receiver
(RCVR)
Receive Clock In
Receive Positive In
Receive Negative In
I
I
I
RCKI[4:1]
RPOSI[4:1]
RNEGI[4:1]
Transmit System Bus
(TSB)
TINDO
TFSYNC
Bused TSB Clock In
I
TSBCKI
TPCMI
O
Bused Time Slot Indicator
Bused TSB Frame Sync
Bused TSB PCM Data In
TSB Signalling In
Transmit Datalink Data In
I
I
I
PIO
TMSYNC[4:1]
TDLCKO[4:1]
PIO TSB Multiframe Sync
TSIGI[4:1]
TDLI[4:1]
Transmit Datalink Clock Out
O
Receive System Bus
(RSB)
RPCMO
RINDO
O
O
Bused RSB PCM Data Out
Bused Time Slot Indicator
Bused RSB Clock In
I
RSBCKI
RFSYNC
RMSYNC
RSIGO
PIO Bused RSB Frame Sync
PIO
RSB Multiframe Sync
PIO RSB Signalling
RDLCKO
RDLO
O
O
O
Receive Datalink Clock Out
Receive Datalink Data Out
Signalling Freeze
SIGFRZ
Boundary Scan
(JTAG)
Test Clock In
Test mode Select
Test Data In
I
I
I
I
TCK
TMS
TDI
TDO
O
Test Data Out
Test Reset In
TRST*
I= Input, O= Output
PIO = Programmable I/O; controls located at PIO (address 018)
100054E
Conexant
1-25
CONEXANT [ CONEXANT SYSTEMS, INC ]
