CX28394/28395/28398
3.0 Registers
Quad/x16/Octal—T1/E1/J1 Framers
3.15 Data Link Registers
0BE—DLINK Test Control #2 or Configuration #2 (DL_TEST5)
Unused bits are reserved and should be written to 0.
7
6
5
4
3
2
1
0
—
DL_TEST5[6]
DL_TEST5[5]
DL_TEST5[4]
DL_TEST5[3]
DL_TEST5[2]
DL_TEST5[1]
DL_TEST5[0]
DL_TEST5[6]
DL_TEST5[5]
DL_TEST5[4]
DL_TEST5[3]
DL_TEST5[2]
DL_TEST5[1]
DL_TEST5[0]
TFIFO2 Read Clear—Force transmit FIFO read pointer to empty.
TFIFO2 Write Clear—Force transmit FIFO write pointer to empty.
TFIFO2 Write—MPU data goes to specified write pointer address.
RFIFO2 Read Clear—Force receive FIFO read pointer to empty state (flush).
RFIFO2 Write Clear—Force receive FIFO write pointer to empty state (flush).
RFIFO2 Write—MPU data goes to specified write pointer address.
RFIFO2 Bypass—Pipe receive data.
100054E
Conexant
3-93
CONEXANT [ CONEXANT SYSTEMS, INC ]
